JPH023343B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving line adapter using a character buffer method.

Generally, as a control method for received data applied to data communication systems, received data from a line is assembled into characters by a line adapter LA.
A method is adopted in which the communication control device LC receives received data from the line adapter LA in character units. This system is schematically shown in Figure 1. In this diagram, PU is the communication control unit
It is a data processing device controlled by LC. In this system, when the communication control device LC receives a special reception character, the processing time for that reception character may temporarily increase.

Even in such a case, in order to receive the subsequent received data normally without overflowing, it is necessary to shorten the character processing time of the communication control device, provide multiple character buffers in the line adapter, or Measures such as providing first-in/first-out memory are being taken. However, among these methods, it is difficult to shorten the character processing time when the bit transmission speed increases, and the method of providing multiple character buffers requires the circuit adapter circuit. The disadvantage is that it increases. Therefore, a method of providing a first-in/first-out shift memory is currently employed.

However, in the method using first-in/first-out shift memory, if there is not a sufficient difference between the bit transmission speed of data received from the line and the speed at which the contents of the first-in/first-out shift memory are retrieved, When the receive character buffer is full, input the receive data bits from the first-in/first-out shift memory to the shift register for assembling the receive character until the communication control device receives the receive data in the receive character buffer. This has the disadvantage that the received data is stored in the first-in/first-out shift memory.

An object of the present invention is to allow data to be read from the line to the first-in/first-out shift memory even when the difference between the bit transmission speed of received data from the line and the speed at which the contents of the first-in/first-out shift memory are taken out is insufficient. It is an object of the present invention to provide a communication control line adapter that can perform high-speed processing by eliminating the accumulation of received data.

According to the present invention, there is provided a first-in/first-out shift memory that sequentially stores received data bits from a line at the bit transmission rate of the line, and a reception character of a required number of bits based on the output of the first-in/first-out shift memory. and a buffer register that temporarily stores the received characters assembled by the shift register, and the received data bits from the line are applied to the shift register via the first-in/first-out shift memory. If the reception character that was assembled immediately before is not picked up by the communication control device and remains in the buffer register, the data is transferred from the first-in/first-out shift memory to the shift register after receiving the required number of bits minus one bit. A line adapter is provided which controls the input of received data bits to be temporarily suspended.

Next, examples of the line adapter according to the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment according to the present invention. Also, Figure 4 shows
This is a time chart for explaining the operation of this embodiment. In this example, 8 bits/character is used. This line adapter includes a first-in/first-out shift memory 1, a shift register 2 for assembling a reception character, a reception character buffer register 3, and a reception control circuit 4. Among these, the first-in/first-out shift memory 1 further includes a first-in/first-out shift memory 1 connected in cascade as shown in the specific example of FIG.
-1 to 1-n. Now, the data bits received from the line are transferred to shift memory 1-1 of the first-in/first-out shift memory.
If the shift memory 1-1 is empty when the received data bits are given, the received data bits are stored at a timing synchronized with the bit transmission rate of the line.

The received data is stored in the first-in/first-out shift memory at the falling edge of the receive clock shown in FIG.

The received data stored in the first-in/first-out shift memory is transferred to the first-in/first-out shift memory.
After waiting for the first-out shift memory 1-2 to become empty, the data is transferred to the first-in/first-out shift memory 1-2. Thereafter, this received data moves each bit of the first-in/first-out shift memory toward the first-in/first-out shift memories 1-n by the same operation.

The reception control circuit 4 changes the state of the first-in/first-out shift memories 1-n and the state of the reception character buffer register 3 (the reception character timing in FIG. 4) at a timing faster than the bit transmission speed of the line (reception character timing in FIG. 4). If the first-in/first-out shift memory 1-n is "full" and the receive character buffer register 3 is "empty", First Inn
The received data bits stored in the first-out shift memory 1-n are input to the shift register 2 for assembling the received character (section 1 in FIG. 4). Immediately after this, when the reception character assembly shift register 2 detects the completion of assembly of one character, it transfers the reception character to the reception character buffer register 3 (timing 3 in FIG. 4). The received character buffer register 3 to which the received character has been transferred does not display an indication that the received character buffer register is "full" until the received character is received by the communication control device LC (see Figure 1). This is done by the reception control circuit 4. The reception control circuit 4 controls when the reception character register 3 is “full”.
And after the required number of bits minus 1 bit, the shift register 2 for assembling the reception character is transferred from the first-in/first-out shift memory 1.
The input of received data bits is prohibited (section 1 in FIG. 4).

To explain the reason for prohibiting the input of received data bits to shift register 2, let us consider, for example, that the bit transmission rate of the line is 48 Kbps and the speed at which the received data stored in the first-in/first-out shift memory is taken over is 48 Kbps. 64Kbps, the required number of bits is 8 bits, the receive character buffer register is "full", and the communication control device LC takes over the contents of the receive character buffer register.
Assuming that it takes 100μS, in the conventional method,
One character time is approximately 166μS at a speed of 48Kbps,
At a speed of 64Kbps, one character takes approximately 124μS. From this, the receive character register becomes "full", the communication control device receives the data, and then the receive character buffer becomes "full".
The time it takes to reach this state is approximately 224.8μS, which is the time it takes for the communication control device to receive data from the receive character buffer register plus the time for one character at a speed of 64Kbps, The character time (approximately 166μS) is exceeded. This means that data is definitely stored in the first-in/first-out shift memory. On the other hand, according to the method of the present invention, under the above assumption, 7 bits have already been entered from the first-in/first-out shift memory into the receive character register, so only the remaining 1 bit needs to be input. About
This is possible in 224.8 μS, and even if the received data is temporarily stored in the first-in/first-out shift memory, there will be no drawbacks like in the prior art.

Furthermore, the point at which input of received data bits is prohibited is set to the required number of bits minus 1 bit.
In order to automatically set the timing at which the receive data is set from the receive character assembly shift register to the receive character buffer register according to the required number of bits, and in the past, when the receive character buffer register becomes "empty", The time from when it becomes "full" to "full" is equal to the speed at which data is taken from the first-in/first-out shift memory x 8 bits (approximately 124.8 μS in the above example) is reduced to 1 bit (approximately 15.6 μS in the above example). ).

In addition, in the above embodiment, when the timing synchronized with the bit transmission rate of the line is output,
If the first-in/first-out shift memory 1-1 is "full" and cannot store received data bits and overflows, the reception control circuit 4 notifies the communication control device LC of the detection of overflow. . Preferably, the capacity of the first-in/first-out shift memory is selected such that the difference between the bit transmission rate of the line and the processing speed of the communication control unit LC does not cause overflow.

As is clear from the above explanation, according to the present invention, there is a sufficient difference between the bit transmission speed of the received data from the line and the speed at which the received data stored in the first-in/first-out shift memory is received. If not, even if the received data from the line may temporarily accumulate in the first-in/first-out shift memory, a simple configuration can prevent the received data from being accumulated in the normal case. Thereby, the effect of improving the processing speed and the economical efficiency of the apparatus is significant.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an outline of a general received data control method applied to a conventional data communication system, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. FIG. 2 is a block diagram showing an example of the structure of the first-in/first-out shift memory, and FIG. 4 is a time chart for explaining the operation of the embodiment shown in FIG. In each figure, 1 is a first-in/first-out shift memory, 1-1 to 1-n are each shift memory stage of the first-in/first-out shift memory, 2 is a shift register for assembling a receiving character, and 3 is a receiving character button. 4 is the reception control circuit, LA is the circuit adapter, LC
is a communication control unit, and PU is a data processing unit.

Claims (1)

[Claims] 1 A first-in/first-out shift memory that sequentially stores data bits received from a line at the bit transmission rate of the line;
A shift register receives the output of the first-out shift memory and assembles it into a required number of reception characters; a buffer register temporarily stores the reception characters assembled by the shift register; When the data is applied to the shift register via the first-out shift memory, while the previously assembled receive character remains in the buffer register without being picked up by the communication control device, the required number of bits minus 1 bit is received. and a reception control circuit for controlling the input of received data bits from the first-in/first-out shift memory to the shift register to be temporarily stopped.