JPS60205650A - Program loading system - Google Patents

Program loading system

Info

Publication number
JPS60205650A
JPS60205650A JP6153484A JP6153484A JPS60205650A JP S60205650 A JPS60205650 A JP S60205650A JP 6153484 A JP6153484 A JP 6153484A JP 6153484 A JP6153484 A JP 6153484A JP S60205650 A JPS60205650 A JP S60205650A
Authority
JP
Japan
Prior art keywords
program
terminal
memory
ipl
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6153484A
Other languages
Japanese (ja)
Other versions
JPH0347541B2 (en
Inventor
Mitsugi Anezaki
姉崎 貢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6153484A priority Critical patent/JPS60205650A/en
Publication of JPS60205650A publication Critical patent/JPS60205650A/en
Publication of JPH0347541B2 publication Critical patent/JPH0347541B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177Initialisation or configuration control

Abstract

PURPOSE:To speed up the rising of the system by sending indication requests for memory block transfer and program loading to a central monitoring device when a part where initial program loading is not performed is accessed. CONSTITUTION:The central monitoring device 2 having received an initial program loading (IPL) request from a terminal 4 reads corresponding blocks out of a storage device 3 according to an IPL data transmission sequence table and sends them out to the terminal 4. Then, it sends an execution instruction for a program during the IPL to the terminal 4 after the blocks corresponding to a block number set in the table are sent out. The monitoring device 2 when receiving a report on the contravention to memory protection before or during the transmission of data with a specific block to the terminal 4 registers the contravention block number in the IPL transmission sequence table at the position of the last specific block number. Then, a memory address for making a restart at the block and number of memory where the contravention to the memory protection is caused by the terminal is sent out to the terminal 4.

Description

【発明の詳細な説明】 (技術分野) である。[Detailed description of the invention] (Technical field) It is.

(従来技術) 従来・ネットワークを介してIPLを行うシステムにお
いては、IPLが完了するまではIPLデータのメモリ
ロードのみを行うため、ネットワ−りのトラクイックが
大きい場合、転送するデータ量が多い場合、akはIP
Lデータの送出する速度が遅い場合においては、非常に
時間がかかシ、また次のIPLデータ受信までの間は何
の処理もしていないことになる。
(Prior art) Conventional systems that perform IPL via a network only load IPL data into memory until IPL is completed, so when the network traffic is large or the amount of data to be transferred is large, , ak is IP
If the sending speed of the L data is slow, it will take a very long time, and no processing will be done until the next IPL data is received.

(発明の目的) 本発明の目的は、ネットワークを介して複数のシステム
にIPLを行う場合において、従来のものの欠4を除去
しシステムの立上シを早くしたIPL方式を提供するこ
とにある。
(Object of the Invention) An object of the present invention is to provide an IPL method that eliminates the deficiencies of the conventional method and speeds up system start-up when performing IPL on a plurality of systems via a network.

(発明の構成) 本発明によると、ネットワークを介してIPLを行なう
時、IPLを受ける装置はあらかじめ定められたブロッ
クごとにメモリの書込みと読出しを禁止する手段を有し
、IPL完了前にIPL途中のプログラムを実行し、I
PLが行われていない部分にアクセスした場合、前記ネ
ットワークに接続された中央監視装置に対しこのメモリ
ブロックの転送及びプログラムロードの滅ための指示要
求を送出することを特徴とするIPL方式が得られる。
(Structure of the Invention) According to the present invention, when performing IPL via a network, a device receiving IPL has means for prohibiting writing and reading of memory for each predetermined block, and Run the program I
An IPL method is obtained which is characterized in that when access is made to a part where PL is not performed, an instruction request to transfer this memory block and terminate program loading is sent to a central monitoring device connected to the network. .

(実施例) 次に、本発明の実施例を図面を参照して説明する。第1
図は本発明が適用されるネットワークの構成図で、1は
データ伝送路、2は中央監視装置、3は記憶装置■、4
〜6は端末である。第2図は本発明において用いる端末
4の内部機能の説明図で、lOは内部データバス、11
は中央制御装置、12はIPLを行うためのROM、1
3はメモリのブロックごとの書込み、読出しを禁止する
ためのメモリプロテクトテーブル、14は該メモリプロ
テクトテーブル15に従いメモリへの書込み、読出しの
禁止ブロックへのアクセス検出回路である。
(Example) Next, an example of the present invention will be described with reference to the drawings. 1st
The figure is a configuration diagram of a network to which the present invention is applied, where 1 is a data transmission path, 2 is a central monitoring device, 3 is a storage device, and 4
-6 are terminals. FIG. 2 is an explanatory diagram of the internal functions of the terminal 4 used in the present invention, where lO is an internal data bus;
is a central control unit, 12 is a ROM for performing IPL, 1
Reference numeral 3 denotes a memory protect table for prohibiting writing and reading of each block of memory, and 14 denotes an access detection circuit for blocks in which writing and reading to the memory are prohibited according to the memory protect table 15.

端末4からの請求を受けた中央監視装置2は、第3図(
a)のIPLデータ送出順序テーブルに従い、記憶装置
3から該轟ブロックを読出し、端末4に送出する。テー
ブルにセットされているブロック数を送出したら、端末
4にIPL中のプログラムの実行命令を送出する。
The central monitoring device 2 receives the request from the terminal 4, and the central monitoring device 2 receives the request from the terminal 4.
According to the IPL data sending order table in a), the block is read from the storage device 3 and sent to the terminal 4. After sending out the number of blocks set in the table, an execution command for the program being IPLed is sent to the terminal 4.

端末4はIPLデータを受信した場合は、転送するブロ
ックのメモリの読書き禁止(メモリプロテクト)を解除
してからメモリへ転送し1ブロツクがすべて転送されて
いない場合は再びメモリプロテクトをセットする。実行
命令を受信した場合は指定のブロックのメモリプロテク
トの解除がある場合は解除して、指定の位置からプログ
ラムを実行する。
When the terminal 4 receives IPL data, it releases the memory read/write prohibition (memory protection) of the block to be transferred and then transfers it to the memory, and if one block has not all been transferred, it sets the memory protection again. When an execution command is received, the memory protection of the specified block is canceled, if any, and the program is executed from the specified position.

IPLしたプログラム実行中にIPLデータを受信した
場合は、前記と同様にメモリに転送した彼、再び実行す
る。実行中にメモリプロテクトに違反した場合は、その
メモリのブロック及び番地を中央監視装置2に通知し、
IPLデータ及び再開指示の受信特に入る◇ 記憶装置3からデータの読出しに時間がかかる場合、又
は端末4からメモリプロテクト違反の通知を受信し、そ
のメモリプロテクト違反したブロックのデータの転送あ
るいは再スタートのための指示送出に時間がかかる場合
は、すでに同一内容を転送した端末に対して端末4にデ
ータの転送を指示する。
If IPL data is received while the IPLed program is being executed, it is transferred to the memory and executed again in the same manner as above. If memory protection is violated during execution, the central monitoring device 2 is notified of the memory block and address;
Reception of IPL data and restart instructions ◇ If it takes time to read data from the storage device 3, or if a notification of a memory protection violation is received from the terminal 4, transfer the data of the block where the memory protection was violated or restart. If it takes time to send an instruction to transfer data, the terminal 4 is instructed to transfer data to a terminal that has already transferred the same content.

端末4に、第3図(a)のブロック番号24のデータ送
出前J民は送出中に、ブロック番号22のメモリプロテ
クト違反の通知を受けた中央監視装置2は、メモリプロ
テクト違反を起こしたブロックの番号を端末4に対する
IPL送出順序テーブルにおいて第3図(b)に示すよ
うブロック番号24の前に登録しなおし、端末4がメモ
リプロテクト違反を起こしたメモリのブロック及び番地
から再スタ以上説明したように、本発明によれば、 f
a’f3ムu−ド時転送するデータ量が多い場合、又は
ネットワークのトラフィックが大きい場合、フ’a7>
AD−ドデータを格納している記憶装置の読出し速度が
遅い場合においてもシステムの立上けを早くすることが
可能となる。
Before sending the data of block number 24 in FIG. 3(a) to the terminal 4, the central monitoring device 2 is notified of the memory protection violation of block number 22. The number is re-registered before block number 24 in the IPL transmission order table for terminal 4 as shown in FIG. 3(b), and terminal 4 restarts from the memory block and address where the memory protection violation occurred. According to the invention, f
a'f3 mode If the amount of data to be transferred is large or the network traffic is large,
Even if the reading speed of the storage device storing AD-code data is slow, it is possible to start up the system quickly.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明が適用されるネットワークの構成因、第
2図は本発明を適用した端末装置の一実施例のブロック
図である。第3図(at(blはIPLデータ送出のメ
モリブロックの順番テーブルである。 1・・・・・・データ伝送路、2・・・・中央監視装置
、3・・・・・・記憶装置、4,5.6・・・・・・端
末、10・・・・・・内部データバス、11・・・・・
・中央制御装置、12・・・・・・ROM、13・・・
・・・メモリグロテクトテープル114・・・・・・ア
クセス検出回路。 ”l(y ′5 凶。
FIG. 1 is a block diagram of the configuration of a network to which the present invention is applied, and FIG. 2 is a block diagram of an embodiment of a terminal device to which the present invention is applied. FIG. 3 (at(bl) is an order table of memory blocks for IPL data transmission. 1...Data transmission path, 2...Central monitoring device, 3...Storage device, 4,5.6...terminal, 10...internal data bus, 11...
・Central control unit, 12...ROM, 13...
...Memory protect table 114...Access detection circuit. ”l(y ′5 evil.

Claims (2)

【特許請求の範囲】[Claims] (1) ネットワークを介してプログラム四−ドを行な
う時プログラムロードを受ける装置はあらかじめ定めら
れたブロックごとにメモリの書込み読出しを禁止する手
段を有し、プログラムロード完了前にプログラムロード
途中のプログラムを゛実行しプログラムロードが行われ
ていない部分にアクセスした場合、前記ネットワークに
接続された中央監視装置に対しこのメモリブロックの転
送及びプログラムロードの再開ための指示要求を送出す
ることを特徴とするプログラムロード方式。
(1) When a program is loaded via a network, the device that receives the program load has means for inhibiting writing and reading of memory for each predetermined block, and the device that is loading the program before the program load is completed. ``When the program is executed and accesses a part where the program load is not performed, the program sends an instruction request to the central monitoring device connected to the network to transfer the memory block and restart the program load. Load method.
(2)中央監視制御装置がプログラムロード中のプログ
ラムロードの再開指示送出要求を受けすぐに応答できな
い場合、再開指示送出完了までは同一内容のプログラム
ロードを行なった他の装置からプログラムロードデータ
の送出全行うことを特徴とする特許請求の範囲第(11
項記載のプデータの送出にあらかじめ定められた時間以
上かかる場合、同一内容のプログラムロードを行なった
他の装置からプログラムロードデータの一送出を行うこ
とを特徴とする特許請求の範囲第(IJJJ記載のプロ
グラムロード方式。
(2) If the central supervisory control device cannot respond immediately to a request to send a program load restart instruction while a program is being loaded, program load data will not be sent from another device that has loaded the same program until the restart instruction is sent. Claim No. (11) characterized in that all
If it takes longer than a predetermined time to send out the program data set forth in Claim 1, the program load data is sent out once from another device that has loaded the same program. Program loading method.
JP6153484A 1984-03-29 1984-03-29 Program loading system Granted JPS60205650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6153484A JPS60205650A (en) 1984-03-29 1984-03-29 Program loading system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6153484A JPS60205650A (en) 1984-03-29 1984-03-29 Program loading system

Publications (2)

Publication Number Publication Date
JPS60205650A true JPS60205650A (en) 1985-10-17
JPH0347541B2 JPH0347541B2 (en) 1991-07-19

Family

ID=13173862

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6153484A Granted JPS60205650A (en) 1984-03-29 1984-03-29 Program loading system

Country Status (1)

Country Link
JP (1) JPS60205650A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10284628B2 (en) 2014-03-12 2019-05-07 Fujitsu Limited Distribution method and resource acquisition method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56105542A (en) * 1980-01-25 1981-08-22 Nec Corp Loading system of program
JPS58146918A (en) * 1982-02-25 1983-09-01 Toshiba Corp Programmable controller

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56105542A (en) * 1980-01-25 1981-08-22 Nec Corp Loading system of program
JPS58146918A (en) * 1982-02-25 1983-09-01 Toshiba Corp Programmable controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10284628B2 (en) 2014-03-12 2019-05-07 Fujitsu Limited Distribution method and resource acquisition method

Also Published As

Publication number Publication date
JPH0347541B2 (en) 1991-07-19

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