JP2507964B2 - Program transfer method - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a plurality of CPUs and CPs.
In a multiprocessor system having an external storage device shared by U, the present invention relates to a program transfer system for transferring a program from the external storage device to each CPU when the system is started up.

[0002]

2. Description of the Related Art In a multiprocessor system having a plurality of CPUs, each CPU is
It has been conventionally practiced to transfer a program (initial program load) from an external storage device shared by each CPU to the local memory of each CPU.

For example, in a multiprocessor system as shown in FIG. 4, a program is transferred as follows. The multiprocessor system shown in FIG. 4 has local memories 42-1 to 42-3.
41-1 to 41-3 having an external storage device, an external storage device 43 having a register 44 and a RAM 45, and a semaphore 4
Common memory 46 provided with 7 and bus arbiter 48
And a common bus 49 that connects the CPUs 41-1 to 41-3, the external storage device 43, and the common memory 46.

When the system is started up, each CPU 41-1 to
41-3 is shown in FIG.
As shown in (1), first, a request to use the common bus 49 is issued to the bus arbiter 48 (step S11).

The bus arbiter 48 has CPUs 41-1 to 41-1.
When a bus use request is added from 41-3, one of them is sent.
One is given the right to use the common bus 49.

Now, for example, the CPU 41-1 uses the common bus 4
If the usage right of 9 is acquired (step S12 is YE
S), the CPU 41-1 tries to acquire the semaphore 47.
(Step S13).

If the acquisition of the semaphore 47 has failed (NO in step S14), the CPU 41-1 returns to the process of step S11, and if successful (step S14).
14 is YES), the program stored in the RAM 45 is transferred to the local memory 42-1 in the own CPU.
(Step S15).

Here, the transfer of the program is specifically performed as follows. That is, the CPU 41-1
First, the upper bit of the start address of the program to be transferred is set in the register 44, and the lower bit is RA.
Give to M45. As a result, the head portion of the program is read from the address indicated by the upper bit and the lower bit of the RAM 45, and C is read via the common bus 49.
It is sent to PU 41-1. The CPU 41-1 stores the head portion of the transmitted program in the local memory 42-1 and abandons the right to use the common bus 49.

After that, the CPU 41-1 requests the bus arbiter 48 to use the common bus 49, and when the right to use the common bus 49 is obtained, the lower bit given to the RAM 45 is incremented by one. This causes the next part of the program to
It is read from the AM 45 and written in the local memory 42-1 in the CPU 41-1. Below, CPU 41-1
Each time the use right of the common bus 49 is obtained, the lower bit given to the RAM 45 is sequentially incremented by 1, and the portion which can be indicated by the upper bit set in the register 44 of the program to be transferred is sequentially transferred. Then, when all the parts that can be indicated by the upper bits are transferred, C
The PU 41-1 updates the high-order address set in the register 44 and sequentially updates the low-order bits given to the RAM 45 in the same manner as described above.

When the program transfer is completed by repeating the above processing, the CPU 41-1 releases the semaphore 47 (step S16).

When the CPU 41-1 releases the semaphore 47, one of the CPUs 41-2 and 41-3 (CPU 41
-2) acquires the semaphore 47 and transfers the program in the same manner as described above. When the program transfer of the CPU 41-2 is completed, the CPU 41-3 acquires the semaphore 47 and transfers the program.

[0012]

The above-mentioned conventional method is
When the system is started up, each CPU constituting the multiprocessor system sequentially transfers the program. Therefore, all the CPUs complete the program transfer and complete the program transfer before the operation state, There has been a problem that the CPU in the operating state has a heavy load for a long time. That is, there has been a problem that the CPU, which has completed the transfer of the program early, becomes heavily loaded for a long time.

It is an object of the present invention to provide a program transfer system capable of preventing a particular CPU from being overloaded for a long time when starting up a multiprocessor system.

[0014]

In order to achieve the above object, the present invention provides a plurality of Cs each having a local memory.
A program transfer method for transferring a program from the external storage device to the local memory of each CPU at the time of system startup of a multiprocessor system including a PU and an external storage device connected to each CPU via a shared bus In the external storage device, a RAM in which a program is stored, a plurality of control registers provided corresponding to each of the CPUs, in which a local memory address, a RAM address and a transfer amount are set, and a fixed amount of An arbitration circuit that determines the CPUs to which the programs are transferred so that the programs are evenly transferred to the CPUs whose transfer amounts are not zero set in the corresponding control registers each time the programs are transferred; By acquiring the right to use the common bus, it corresponds to the CPU determined by the arbitration circuit. Based on the local memory address and the RAM address set in the control register, the fixed amount of the program is transferred from the RAM to the local memory in the CPU determined by the arbitration circuit, and the content of the control register is updated. Each of the CPUs acquires a right to use the common bus when the system is started up, thereby setting a local memory address, a RAM address and a transfer amount in the control register corresponding to the own CPU. It is configured as follows.

[0015]

When the system is started up, each CPU acquires the right to use the common bus, and the local memory address, RAM address,
Set the transfer amount.

The arbitration circuit serves as a program transfer destination so that the program is transferred evenly to CPUs whose transfer amount set in the corresponding control register is not zero each time a fixed amount of the program is transferred. Become C
Determine the PU.

When the transfer circuit acquires the right to use the common bus, the transfer circuit acquires the local memory address and the RAM set in the control register corresponding to the CPU determined by the arbitration circuit.
C determined by the arbitration circuit from the RAM based on the address
A certain amount of program is transferred to the local memory in PU, and the content of the corresponding control register is updated.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, which includes a plurality of CPUs 1-1 to 1-3 and an external storage device 4.
, Common memory 9, bus arbiter 10, and common bus 1
1 and 1.

The external storage device 4 and the common memory 9 can be accessed from each of the CPUs 1-1 to 1-3 through the common bus 11.

Each of the CPUs 1-1 to 1-3 has its own local memory 2-1 to 2-3 and its own CPU 1-1 to 1-3.
Register 3-1 to 3-3 in which the CPU numbers of the above are set.

The external storage device 4 has CPUs 1-1 to 1-
3 has control registers 5-1 to 5-3, an arbitration circuit 6, a transfer circuit 7, and a RAM 8 storing a program to be transferred to each of the CPUs 1-1 to 1-3.

Control register 5-corresponding to CPU 1-1
2, the first address (local memory address) 51-1 of the program storage portion in the local memory 2-1 and the program stored in the RAM 8 are transferred to the CPU 1-1. The start address (RAM address) 52-1 of the program to be executed and the number of transfer bytes 53-1 are set. Control register 5-2, 5
Similar information is set for -3. In the following description, the local memory address, RAM address, and transfer byte number set in the control register 5-i (1≤i≤3) are 51-i, 52-i, and 53, respectively.
-I.

The arbitration circuit 6 has a function of determining a CPU to transfer a program in a round robin method for each data transfer cycle and instructing the transfer circuit 7 to transfer the program to the CPU. Have. In this embodiment, it is assumed that one byte of program is transferred in one data transfer cycle.

The transfer circuit 7 has a function of transferring one byte of the program stored in the RAM 8 to the local memory in the instructed CPU when the transfer of the program is instructed by the arbitration circuit 6.

FIG. 3 is a flow chart showing a processing example of the CPUs 1-1 to 1-3, and the operation will be described below with reference to each drawing.

At system startup, each CPU 1-1 to 1
In order to perform the initial program loading, -3 requests the bus arbiter 10 to use the common bus 11 as shown in FIG. 3 (step S1).

The bus arbiter 10 has CPUs 1-1 to 1-1.
When a usage request is made from -3, the usage right of the common bus 11 is given to one of them.

Now, for example, the common bus 11 to the CPU 1-1
If the right to use is given (step S2), the CP
U1-1 reads the contents of register 3-1 and uses its own CPU
To obtain the CPU number (step S3).

Thereafter, the CPU 1-1 causes the external storage device 4 to
Among the control registers 5-1 to 5-3 in the above, to the control register 5-1 corresponding to the CPU number acquired in step S3,
Local memory address 51-1, RAM address 52
-1 and the number of transfer bytes 53-1 are set, and the common bus 1
The usage right of 1 is abandoned (step S4).

The arbitration circuit 4 includes control registers 5-1 to 5-
The number of transfer bytes 53-1 to 53-3 of 3 is circularly referenced, and the number of transfer bytes is not "0".
When i is detected, the control register 5-
It is instructed to transfer 1 byte of the program to the local memory 2-i in the CPU 1-i corresponding to i. In this example, since only the transfer byte number 53-1 of the control register 5-1 corresponding to the CPU 1-1 is not “0”, the arbitration circuit 4 instructs the transfer circuit 7 to transfer the local memory in the CPU 1-1. It will instruct to transfer the program to 2-1.

Upon receiving this instruction, the transfer circuit 7 requests the bus arbiter 10 to use the common bus 11.

At this time, the bus arbiter 10 has a CPU 1
Since the usage requests from -2 and 1-3 are already added, the usage right of the common bus 11 is not given to the transfer circuit 7, but the usage right is given to the CPU 1-2 or the CPU 1-3. .

CPU to which the right to use the common bus 11 is given
1-2 or the CPU 1-3, like the CPU 1-1 described above, stores the local memory address, the RAM address, and the transfer byte number in the control registers 5-2 and 5-3 corresponding to the own CPUs 1-2 and 1-3. Set (steps S1 to S
4).

As described above, all CPUs 1-1 to 1-1
When the local memory address, the RAM address, and the number of transfer bytes are set in the control registers 5-1 to 5-3 corresponding to 1-3, the bus arbiter 10 gives the transfer circuit 7 the right to use the common bus 11.

When the transfer circuit 7 is given the right to use the common bus 11, the CPU 1-instructed by the arbitration circuit 6
In order to transfer the program to the local memory 2-1 in 1, the control register 5-1 corresponding to the CPU 1-1 is referred to.

The RA indicated by the RAM address 52-1 set in the control register 5-1
The program extracts one byte from the address of M8 and outputs it to the common bus 11, and outputs the local memory address 51-1 set in the control register 5-1 to the common bus 11. As a result, the 1-byte program fetched from the RAM 8 is stored in the local memory 2
Written to -1.

After that, the transfer circuit 7 controls the control register 5-
Local memory address set to 1 51-
1, the RAM address 52-1 is incremented by 1 and the transfer byte number 53-1 is decremented by -1. Further, the transfer circuit 7 relinquishes the right to use the common bus 11 and notifies the arbitration circuit 6 that the transfer of the program of 1 byte is completed.

Upon receiving this notification, the arbitration circuit 6 controls the control register 5-2 next to the control register 5-1 referred to previously.
Refer to. At this time, since the number of transfer bytes 53-2 set in the control register 5-2 is not "0", the arbitration circuit 6 sends the transfer circuit 7 the local register in the CPU 1-2 corresponding to the control register 5-2. It is instructed to transfer a 1-byte program to the memory 2-2. If the number of transfer bytes set in the control register 5-2 53-
If 2 is “0”, the arbitration circuit 6 sends the next control register 5
-3, the same processing is performed.

When the above instruction is received from the arbitration circuit 6,
The transfer circuit 7 is a control register 5-corresponding to the CPU 1-2.
1 byte of program RAM based on the contents of 2
8 to the local memory 2-2 in the CPU 1-2.

Thereafter, the same processing as described above is repeated, and the program is cyclically transferred byte by byte to each of the CPUs 1-1 to 1-3. If there is a CPU that has finished transferring the program, the number of transfer bytes set in the control register corresponding to that CPU is “0”, and the arbitration circuit 6 transfers the program to the CPU. 7 is not instructed, the program is cyclically transferred byte by byte to CPUs other than the CPU whose transfer has been completed.

When the number of transfer bytes set in each of the control registers 5-1 to 5-3 becomes "0", the transfer of the program to all CPUs is completed.

[0043]

As described above, according to the present invention, each CP
The program is transferred to U in parallel, and the variation in the operation start time (transfer completion time of the program) of each CPU can be reduced. This has the effect of preventing the CPU (CPU that has entered the operating state quickly) from becoming heavily loaded for a long time.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of contents of a control register 5-1.

FIG. 3 is a flowchart showing a processing example of CPUs 1-1 to 1-3.

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is a flowchart showing a processing example of CPUs 41-1 to 41-3.

[Explanation of symbols]

 1-1 to 1-3, 41-1 to 41-3 ... CPU 2-1 to 2-3, 42-1 to 42-3 ... Local memory 3-1 to 3-3, 44 ... Register 4, 43 ... External storage device 5-1 to 5-3 ... Control register 6 ... Arbitration circuit 7 ... Transfer circuit 8, 45 ... RAM 9, 46 ... Common memory 10, 48 ... Bus arbiter 11, 49 ... Common bus 47 ... Semaphore

Claims (2)

(57) [Claims] 1. A multiprocessor system comprising a plurality of CPUs each having a local memory, and an external storage device connected to each CPU via a common bus. Each CP
In a program transfer method for transferring a program to a U local memory, the external storage device is provided corresponding to each of the RAM for storing the program and each of the CPUs, and has a local memory address, a RAM address and a transfer amount. Each time a certain amount of program is transferred and a plurality of control registers to be set, the transfer amount set in the corresponding control register is not zero CP
An arbitration circuit that determines the CPU to which the program is transferred so that the programs are transferred to U evenly, and a control corresponding to the CPU that is determined by the arbitration circuit by acquiring the right to use the common bus. Based on the local memory address and the RAM address set in the register, the fixed amount of the program is transferred from the RAM to the local memory in the CPU determined by the arbitration circuit, and the content of the control register is updated. Each of the CPUs acquires a right to use the common bus when the system is started up, and sets a local memory address, a RAM address and a transfer amount in the control register corresponding to the own CPU. A program transfer method characterized in that 2. A local memory address set by each CPU in the control register corresponding to its own CPU is
2. The program transfer method according to claim 1, wherein a start address of a program storage portion of a local memory in the own CPU is shown, and a RAM address is a start address of a program to be transferred from the RAM.