JPS62214442A - Instruction advance reader - Google Patents

Abstract

PURPOSE:To shorten the time required for instruction advance read and to increase the processing speed by transferring an address from a central processing unit to a main memory device only in case of execution of branch instructions and making it unnecessary to transfer the address at every time of data storage in an IBR storage circuit in the other cases. CONSTITUTION:When a branch instruction is executed by a central processing unit a, an ICR branch instruction signal line 16 from an ICR storage circuit 1 and an IBR empty signal line 13 from an IBR storage circuit 2 are made conductive, and an ICR transfer instruction signal line 10 from an IBR empty control circuit 9 is made conductive. Thus, a SUBICR storage instruction signal line 17 from an SUBICR control circuit 8 is made conductive, and the address outputted from the ICR storage circuit 1 to an address data bus signal line 12 is fetched into an SUBICR storage circuit 7. Next, a data read instruction signal line 18 is made conductive, and the address stored in the SUBICR storage circuit 7 is updated to read out data in a main memory device B.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is characterized in that a central processing unit and the above tα device are connected via a data bus, and instructions pre-read from a main memory are stored in an instruction buffer and executed. The present invention relates to an information processing system, and particularly to a technique for pre-reading the instructions.

[Conventional technology]

Conventionally, an instruction advance reading device in this type of information processing system has an address register on the central processing unit side that indicates the address of an instruction to be read in advance, and the contents of the address register are read every time an instruction read request is made. A configuration was adopted in which data was sent to the main storage device.

FIG. 4 is a block diagram of a conventional instruction advance reading device;
The figure is the operation timing chart, and 8 is the ICR
(Instruction Counter Regi
ster) Storage circuit 1. The instruction buffer [B R
(InstructionBuffer Register
er) Storage circuit 2. IBR control circuit 3 and PFI
C (Prefetch In5truction Co.
B) a central processing unit having a register circuit 6;
are data register circuit 4 and address register circuit 5
This is the main memory containing the .

The TCP storage circuit 1 of the central processing bag mA stores an instruction address used for executing a macro instruction, and the storage address is applied to the PFIC register circuit 6 via an ICR data signal line 15. The ll3R storage circuit 2 stores a plurality of macro instructions pre-read from the main memory B via the address data bus signal line 12, and when an empty space occurs in the storage area, the level of the IBR empty signal line 13 is changed to a logic level. The flag is set to "1" (hereinafter simply referred to as "1") and the IBR control circuit 3 is notified of this fact. When the IBR empty signal line 13 identifies that a vacant space has occurred in the IBR storage circuit 2, the IB Rtll control circuit 3 sets the ICR transfer instruction signal line 10 to "1" and sends the signal to the address register circuit 5 of the FI WB. The IBR control circuit 3 alternately instructs the data transfer signal line 11 to take in the address, and sets the data transfer signal line 11 to "1" to instruct the data register circuit 4 of the main memory B to send the stored data. By setting the PF[C update instruction signal vA14 to "1", the PF
[PFIC register circuit 6 in C register circuit 6] Instructs PFIC register circuit 6 to update the value of the C register. P.F.
The IC register circuit 6 stores an instruction address for storing an instruction in the IBR storage circuit 2 in an internal PFIC register, and transmits this to the address register circuit 5 of the main memory B via the address data bus signal line 12. It is a circuit for transmitting data, and when an update instruction is received from the IBR control circuit 3 through the PFIC update instruction signal m14, the contents of the PFIC register are updated.

Further, the data register circuit 4 in the main memory device B is a circuit that holds data read out from the main memory device B according to the address held in the address register circuit 5, and the held data is stored when the data signal line 11 is ” is output to the address data bus signal line 12 at a predetermined timing. The address register circuit 5 is a PFI of the central processing bag mA.
This circuit takes in the address sent from the C register circuit 6 via the address data bus signal line 12 at a predetermined timing when the IcR transfer instruction signal line IO becomes "L". When a new address is taken in, the data of 7 addresses of main memory B corresponding to the address is read out and set in the data register circuit 4.

Now, each part in FIG. 4 is connected to the three types of clocks To shown in FIG.
, TI, and T2, and the address access time of main memory B is 3T. If a vacant space occurs in the IBR storage circuit 2 at a certain point, the IBR storage circuit 2 operates in synchronization with the IBR vacant signal line 13. Set “1” to IBRi! The l1m circuit 3 is notified of this fact. When the IBR control circuit 3 detects that the IBR empty signal line 13 becomes "L", the PFI
The C update instruction signal line 14 is set to 1'' from the immediately following clock T2 to the next clock T2, and the PFIC register circuit 6
In response to this, the PFIC is activated at the timing of the clock TO.
The address of the register is updated, and the updated address value n is output to the address data bus signal line 12 from clock To to the next clock TO. Further, the IBR control circuit 3 causes the address register circuit 5 to take in the address outputted to the address data bus signal line 12.
■CR transfer instruction signal line 10 from clock TO to next clock T.

up to “1”.

When the CR transfer instruction signal line 10 becomes "1", the address register circuit 5 of the main memory device B takes in the address on the address data bus signal line 12 at the timing of the clock T1, and then takes in the address in the main memory device B. The data Dn stored at the address corresponding to the address (in the case of an 1 word instruction, this data Dn becomes 1 instruction) is read out and set in the data register circuit 4 at the timing of the next clock T1.

Next, in order to transfer the data Dn set in the data register circuit 4 to the central processing unit A, the IBR control circuit 3 sets the data transfer signal line 11 to "1" from clock TO to the next clock TO. As a result, the data register circuit 4 becomes output enabled and outputs the data Dn to the address data bus signal line 12, and the IBR storage circuit 2 receives the clock T2 whose data transfer signal line 11 is "1".
The data Dn outputted to the address data bus signal line 12 at the timing of is stored.

If there is still space after storing the data Dn, the IBR storage circuit 2 holds the IBR empty signal line 13 at "L" as shown in FIG.
The control circuit 3 is notified. Therefore, P
The PFIC register of the FIC register circuit 6 is updated again with the clock To, and the value n+1 is output to the address data bus signal line 12, and the ICR transfer instruction signal line 10 from the IBR control circuit 3 becomes "L" again. , Therefore, the instruction address fi+l is set in the address register circuit 5 of the main memory B again, the data Dn+1 read from the main memory B is set in the data register circuit 4, and the data transfer from the I[3R control circuit 3 Signal line 11
becomes 1', data Dn+1 is set in the IBR storage circuit 2 at the timing of the clock To. FIG. 5 shows an example in which there is no free space in the IBR storage circuit 2 at this point, and the level of the IBR empty signal line 13 of the IBR storage circuit 2 is set to logic "0" (hereinafter simply referred to as "0") at clock T2. ).

[Problem that the invention seeks to solve]

As mentioned above, in the conventional instruction advance reading device, the PFI of the PFIC register circuit 6 provided on the central processing unit A side
It is necessary to send the address contents of the C register to the main storage device B each time data is to be stored in the BR storage circuit 2, which has the disadvantage that the processing time for advance reading of an instruction is long.

The present invention solves these conventional drawbacks, and its purpose is to transfer the address from the central processing unit to the main memory only when a branch instruction is executed, and to transfer the address from the central processing unit to the main memory in other cases. B
I? By eliminating the need to transfer an address every time data is to be stored in a path, the time required for instruction advance reading is reduced and processing speed is improved.

[Means for solving problems]

In order to achieve the above object, the instruction pre-reading device of the present invention reads instructions to be executed by a central processing unit from a main storage device and stores them in an instruction buffer prior to execution. In the apparatus, on the central processing unit side, an ICR storage means for storing an instruction address used in the execution of an instruction by the central processing unit, and an IBR storage unit for storing a plurality of instructions pre-read from the main storage device. means, when a vacant space occurs in the IBR storage means, if there is a branch instruction from the ICR storage means, requesting the main storage device to fetch the branch destination instruction address stored in the ICR storage means, and then retrieving the branch destination instruction address from the ICR storage means; A data request is made to the storage device until the IBR storage means is full, and the IC
If there is no branch instruction from the R storage means, data requests are made to the main storage device until the IBR storage means is full without issuing a request to fetch the address.
BI? The empty control semi-control means and a SUBICR (S) for storing an address to be pre-read on the main memory side.
ub In5truction Counter Re
a data register means for storing data in the main memory device read by the address stored in the SUB ICR storage means; and a branch destination instruction address capture request from the IBR empty control means. In response to this, the branch destination instruction address sent from the ICR storage means of the central processing unit is stored in the SUBICR storage means, and in response to a data request from the IBR idle control etc. control means, the branch destination instruction address is stored in the data register means. S sends the set data to the IBR storage means and updates the storage address of the SUBICR storage means.
It has a configuration including a UBICR control means.

[Effect]

If the execution of instructions in the central processing unit is sequential without including a branch, the address of the instruction to be pre-read will also be sequential, but if a branch is included, it is necessary to pre-read from the address of the branch destination. Therefore, if an empty space occurs in the IBR storage means when a branch instruction is executed in the central processing unit and an instruction to that effect is issued from the ICR storage means, the BR empty control means first sends the branch destination address to the SUB
A request to take in the branch destination instruction address is issued to the tα device to store it in the ICR storage means. In response, the SUBICR control means on the main memory side stores the branch destination instruction address of the ICR storage means in the SUBICR storage means. IBI? After completing the empty controller control means, it issues a data request to the main memory. This data request is processed by the SUBICR control means on the main storage side, and the 5UBrCR
The control means is the SUB I stored in the data register means.
The data corresponding to the storage address of the CR storage means is sent to the IBR storage means on the central processing unit side, and the address stored in the SUBICR storage means is updated in preparation for the next data request.

When the execution of instructions in the central processing unit is sequential without branching, and an empty space occurs in the IBR storage means, the address to be read next is held in the SUB ICR storage means on the main memory side. And 5UBI6R
Since the addresses are sequentially updated by the control means in synchronization with advance reading, the TBR empty control means can simply issue a data request to the main storage device until the IBR storage means is full, and the necessary data can be stored without transferring the address. Data or instructions are read from main memory and stored in the IBR storage means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which the same reference numerals as in FIG. 4 indicate the same parts, 7 is a SUBICR storage circuit, 8 is a SUBICR control circuit, 9 is an IBR empty control circuit, and 16 is an ICR A branch instruction signal line, 17 is a SUBICR storage instruction signal line, and 18 is a data read instruction signal line.

2 and 3 are operation timing charts of FIG. 1, and in FIG. 2, a branch instruction is executed in the central processing unit A, and at that time, there are 2 words vacant in the IBR storage circuit 2. FIG. 3 shows a timing chart when two words become vacant again in the IBR storage circuit 2 after the processing shown in FIG. 2.

In FIG. 1, an ICR storage circuit 1 stores an instruction address for executing a macro instruction. When a branch instruction is executed on the central processing unit side, the ICR storage circuit 1 sends the branch destination address through an address data bus signal 'a12. At the same time as outputting to the SUBICR storage circuit 7, the ICR branch instruction signal line 16 connected to the IBR empty control circuit 9 is set to "1" from clock T2 to the next clock T2, and this fact is output to the IBR
The empty control circuit 9 is notified.

The IBR storage circuit 2 stores a plurality of macro instructions from the main memory B, and this storage is performed by the IBR empty control circuit 9.
This is performed at the timing of clock T2 when the data transfer signal line 11 connected to the signal line 11 becomes "L". In addition, when the IBR storage circuit 2 becomes vacant in its storage area, the IBR storage circuit 2
Set the IBR empty signal line 13 connected to the empty control circuit 9 to “1”
and notifies the IBR empty control circuit 9 of this fact.

The IBR empty control circuit 9 sends a request to the main memory B to fetch the branch destination address stored in the ICR storage circuit 1;
It requests the transmission of data set in the data register circuit 4, and specifically performs the following operations. That is, when the IBR empty signal line 13 connected to the IBR storage circuit 2 becomes "1", the ■CR branch instruction signal line I6
If is "l", the ICR transfer instruction signal line 10 connected to the SUBICR control circuit 8 from clock TO to the next clock To is set to "1" as shown in FIG. The data transfer signal line 11 connected to the SUBICR control circuit 8 and the IBR storage circuit 2 is set to "1" for a period corresponding to the number of empty words of 2, and when the IBR empty signal line 13 becomes "1". , I
If the CR branch instruction signal 'kA16 is "O", the ICR transfer instruction signal line 10 is not set to "1" as shown in FIG. The data transfer signal line 11 is set to "1" only during this period.

Further, the SUBICR$I+ control circuit 8 controls the storage of the branch destination address in the SUBICR storage circuit 7, the updating of this stored address, and the output enable of the data register circuit 4. That is, when the TCP transfer instruction signal line 10 becomes "1", SUBI is
The 5tJB ICR storage instruction signal line 17 connected to the CR storage circuit 7 is set to "1", and the data transfer signal line 11 is set to "1".
When becomes “I”, SUBICR is used for the period of “l”
The data read instruction signal line 18 connected to the storage circuit 7 and data register circuit 4 is set to "1".

The SUBICR storage circuit 7 is connected to the address data bus signal line 12, the 5UI31CR storage instruction signal line 17, and the data read instruction signal line 18, and when the SUBICR storage instruction signal line I7 becomes "I", ICR storage is performed at the timing of the clock T1. Address data bus signal line 1 from circuit l
Stores the branch destination address added via 2. Note that when the address is stored in the SUB I CR storage circuit 7,
Data in main memory B corresponding to that address is read out and applied to data register circuit 4. Also, S.U.
After the instruction corresponding to the stored address is read out, the BICR storage circuit 7 sets the data read instruction signal line I8 to “1”.
”, the stored address is updated at the timing of clock T1.

The data register circuit 4 is a circuit that holds read data from the main memory device B, and outputs the held data onto the address data bus signal 3812 at the timing of the clock T1 when the data read instruction signal line 18 is '1''.

Next, with reference to FIG. 2, in the configuration of FIG. 1, a branch instruction is executed in central processing unit A, and at that time,
The operation of this embodiment will be explained by taking as an example the case where there are two words available in the storage circuit 2.

Each part in Figure 1 is connected to the three types of clocks TO and Tl shown in Figure 2.
, T2, and the address access time of main memory B is 3T. Here, central processing unit A
When a branch instruction is executed, the content of the address outputted from the ICR storage circuit 1 to the address data bus signal line 12 from clock TO to the next clock To is, for example, the address n of the branch destination in the case of an unconditional branch. , also I
The CR storage circuit 1 sets the ICR branch instruction signal line 16 to '1' from clock T2 to the next clock T2.

Furthermore, since the IBR storage circuit 2 has become vacant,
IBR empty signal line 13 to 11 at the timing of clock T2
shall be.

When the IBR empty control circuit 9BR empty signal line 13 becomes "1" and the ICR branch instruction signal line 16 becomes "1", the ICR transfer instruction signal line 10 is first set to "1" at the timing of clock TO.

When the ICR transfer instruction signal line 10 becomes "1", the SUBICR control circuit 8 controls the SUBICR control circuit 8 only during that "1".
The R storage instruction signal line 17 is set to °l'', and the SUBICR storage circuit 7 responds to this by setting the 5tJBICR storage signal line 17.
ICR storage time F at the timing of clock T1 when is “L”
Address n outputted from aI to address access time [12] is fetched internally. By storing this new address, the above t (data Dn of device B) corresponding to the address is read out.

Next, IBR air control type control circuit 9 ICR transfer instruction signal branch line 10
■CR at the timing of the next clock To after setting it to “L”
The levels of the branch instruction signal line 16 and the IBR empty signal line 13 are identified. In the case of FIG. 2, there is only one branch and the ICR branch instruction signal line 16 is "0" at that time, and the IBR empty signal line 13 is 1'', so the IBR air control type control circuit 9 ICR transfer instruction The signal line 10 is set to "0" and the data transfer signal line 11 is set to "11".

When the data transfer signal line 11 becomes 11 as described above, the 5UBTCR control circuit 8 sets the data read instruction signal line 18 to ``15'' only during the period 1''. In response to this, the data register circuit 4 outputs 5UBII? at the timing of clock T1. The data Dn read from the address stored in the storage circuit 7 is held and outputted to the address data bus signal line 12, and the IBR storage circuit 2 receives the data at the timing of the clock T2 when the data transfer signal &'J111 is 1''. The data Dn is stored. Furthermore, when the data read instruction signal line 18 becomes 1", the SUBICR storage circuit 7 updates the internally stored address n to fi+l, and the data Dn+1 of the main memory B at the address n+l. will then be read out.

IBR air control control circuit 9 data transfer signal cotton 11 “1”
At the next clock TO timing, I
The levels of the CR branch instruction signal 16 and the IBR empty signal line 13 are identified. FIG. Since the IBR air control control circuit 9 holds the signal "l", it outputs "l" subsequent to the data transfer signal NlAl1. For this reason, SUB I CR11? ! 1 circuit 8 sets the data read instruction signal line 18 to "1" as described above.
By setting the data register circuit 4 hair address f
The data Dn+1 corresponding to i+l is set, the data Dn+l is output to the address data bus signal line 12, and the storage address n+l of the SUBICR storage circuit 7 is updated to n+2. Then, the I[3R storage circuit 2 stores the data Dn+1 output to the address data bus signal line 12, and since the area of the IBR storage circuit 2 is now full, the IBR empty signal line 13 is set to "0". . Therefore, if the level of the IBR air control signal line 13 is identified at the timing of the clock To of the IBR air control circuit 9, “
Since it is "0", the data transfer signal line 11 is reset to "0".

In this state, the SUB I CR storage circuit 7 stores address n+2 to be pre-read next when sequential instruction execution is performed.

In this way, in this embodiment, when a branch instruction is executed, the address n given by the branch instruction is stored in the main memory B only once.
If the address n+1 is transferred to the upper storage device WB, there is no need to transfer the address n+1 necessary for preliminary reading of the subsequent data Dn+l and the like to the upper storage device WB. Further, since the address of the next instruction to be pre-read is stored in the SUBICR storage circuit 7, the instructions are executed sequentially, and then l
When the BR storage circuit 2 becomes vacant, the central processing unit A
All that is required is to request data from the main storage device B from the main storage device B. That is, as shown in Fig. 3, two SUB I C
Since the address n+2 is stored in the R storage circuit 7, when, for example, two words become vacant in the IBR storage circuit 2 and the IBR vacant signal line 13 becomes 1'', the IBR vacant control circuit 9CR branch instruction signal is output. Since line 16 is 0'',
While keeping the ICR transfer instruction signal 10 at “θ”, the data transfer signal line 11 is set to “1°.” This data transfer signal line 11
The operation after becomes "1" is the same as in the case of FIG. 2, and as a result, data [)n+2 corresponding to address n+2 and data Dn+3 corresponding to address n+3 are stored in the IBR storage circuit 2. , the IBR storage circuit 2 is filled. Then, fi+4 is kept stored in the SUBICR storage circuit 7 as the next address to be pre-read.

〔Effect of the invention〕

As explained above, in the present invention, when there is a vacant space in the IBR storage means and there is a branch instruction from the ICR storage means, the data request is made after requesting the main memory to fetch the branch destination instruction address, and the branch If there is no instruction, the central processing unit is provided with an IBR empty control means that makes a data request to the main memory without issuing an address capture request, and the main memory side is provided with a branch destination instruction address of the TBR empty control etc. control means. 5LJB I in response to the import request
Storing a branch destination instruction address from the central processing unit in the CR storage means, and sending the instruction set in the data register means to the central processing unit in response to a data request.
SUBICR$t+I? to update the address stored in the BTCR storage means? n means, the address transfer from the central processing unit to the main memory is only required when a branch instruction is executed; in other cases, a data request without address transfer is sufficient; This has the effect of shortening the time required for processing and improving processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
An operation timing chart when a branch instruction is executed in the central processing unit A in the configuration shown in the figure and there are two words available in the IBR storage circuit 2 at that time. Storage circuit 2
FIG. 1 is an operation timing chart of FIG. 1 when two words are vacant, FIG. 4 is a block diagram of the conventional example, and FIG. 5 is an operation timing chart of FIG. 4. In the figure, 1...ICR storage circuit, 2...IBR
Storage circuit, 3... IBR control circuit, 4... Data register circuit, 5... Address register circuit, 6...
PFIG register circuit, 7-- SUBICR storage circuit, 8-- SUBICR control circuit, 9-- Bow/BR empty control circuit, 10-- ICR transfer instruction signal line, 11--
Data transfer signal line, 12...Address data bus signal line, 13...■13R empty signal line 14...PFIC
Update instruction signal line, 15...ICR data signal line, 16
...ICR branch instruction signal line, 17...SUBICR
Storage instruction signal line, 18...Data read instruction signal line.

Claims (1)

[Scope of Claim] In an instruction advance reading device for an information processing system that reads an instruction to be executed by a central processing unit from a main memory and stores it in a read instruction buffer prior to its execution, on the side of the central processing unit, the above-mentioned an ICR storage means for storing an instruction address used for executing an instruction in a central processing unit; an IBR storage means for storing a plurality of instructions pre-read from the main memory; and a vacant space in the IBR storage means. At this time, if there is a branch instruction from the ICR storage means, the main storage device is requested to fetch the branch destination instruction address stored in the ICR storage means, and then the IBR storage means is full. Data requests are made until the IC
If there is no branch instruction from the R storage means, data requests are made to the main storage device until the IBR storage means is full without issuing a request to fetch the address.
BR empty control means, and SUBICR storage means for storing an address to be pre-read on the main storage side; and data in the main storage device read by the address stored in the SUBICR storage means. data register means for storing a branch destination instruction address sent from the ICR storage means of the central processing unit in the SUBICR storage means in response to a branch destination instruction address capture request from the IBR empty control means; S transmitting the data set in the data register means to the IBR storage means in response to a data request from the IBR empty control means, and updating the storage address of the SUBICR storage means.
1. An instruction advance reading device comprising a UBICR control means.