JPS60211559A - Common memory control system - Google Patents

Abstract

PURPOSE:To use more efficiently a memory by adding a specific code before and after a data to be changed to prevent competition when the memory is used in common asynchronously and a computer revises the content of the memory. CONSTITUTION:When the compter rewrites the data of the memory MEM, the specific code (SKIP and END) is added before and after the data to be modified and the result is transmitted to a data bus so as to revise the content of the memory. When the specific code SKIP is detected by a decoder section 13, it is transferred to a transfer control section 14, which stops the transfer of data. When the revision of the memory is finished, the decoder section 13 detects the specific code END, gives it to the control section 14, which restarts the data transfer. In this case, an address signal outputted by an address counter section 16 is not affected by the stop of data transfer. Further, the computer can revise optionally the content of memory as required. Thus, the competition of the use of the memory is prevented and the memory is used more efficiently.

Description

[Detailed Description of the Invention] Technical field to which the invention pertains The present invention relates to a computer and a data transfer circuit (DMA etc.)
This invention relates to a common memory control method for controlling data access conflicts when a common memory is used asynchronously.

BACKGROUND ART Conventionally, when using this type of common memory, in order to prevent contention for the memory, while one device is using the memory, the other device is simply controlled to wait for the other device to access the memory. However, in the conventional method of 1.6, if the data transfer circuit is designed to transfer data periodically, such as when refreshing a CR7 screen, the refresh timing will be disrupted due to waiting for memory access. There are drawbacks. Furthermore, on the data transfer side, there is also the inconvenience that the computer or memory cannot be used even during a WAIT state in which data transfer is suspended due to the processing capacity of an external device.

[1] An object of the present invention is to solve the above-mentioned conventional drawbacks, and to prevent conflicts in memory use without disrupting each timing when memory is used in common asynchronously, thereby making it more efficient. The goal is to realize efficient memory usage.

Composition of the Invention The common memory control method of the present invention is a transfer control method that transfers data stored in a memory connected to a computer to the outside asynchronously with the computer. In the common memory control system with porridge, the computer adds a special code before and after the data being changed and sends it on the data bus, and decodes the data on the data bus to detect the special code. The data transfer control section is characterized in that the transfer control section stops or restarts the data transfer operation according to an output signal of the message decoder section.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

Figure i1 is a block diagram showing one embodiment of the present invention.

That is, a memory HEM connected to a data bus, a transfer control unit 14 that transfers data in the memory by DMA, and a special code (SKI) that decodes messages on the data bus.
The message decoder section 11 sends a signal indicating the information to the transfer control section I4 to control its operation when it detects the P and EN code. Transfer control unit 14
consists of hardware logic such as a buffer section 15 for outputting messages to an external device and an address counter section 16 for determining the address to be transferred from the memory MEH. It uploads the data, takes out the data, and outputs it from the 4777 section 15 to an external device.

The message decoder section 11 decodes the register section 12 for holding the digital data 101 on the data bus "2" and the output of the register section 12, and upon detecting a special code, sends the information to the transfer control section 14. It consists of hardware logic of a decoder section 13AJ.

When the transfer control section 14 receives a SKIP signal from the message decoder section 11 during normal transfer operation,
The data transfer from the 4777 unit 15 to the outside is stopped +1-. However, the address counter FiR18 continues its count-up operation as usual. Next, upon receiving the END signal from the message decoder section 11, the normal transfer operation is resumed. At this time, address counter section I6 1'
Since the input address signal is the same as if the data transfer had not been carried out, the timing of the transferred data will not be disrupted by stopping the data transfer.

Next, the operation of the tree embodiment will be explained. The normal transfer operation is as described above, but when rewriting data in the computer or memory HEM, special codes (SKIP and END) are added before and after the changed data, as shown in Figure 2.
) and sends it onto the data bus to update the memory contents. Special code 5KIP or decoder section 13 mentioned above
When detected, the information is sent to the transfer control unit 14, and the transfer control unit 14 stops the data transfer. Therefore, the data being changed is not sent to the outside. However, the address counter section 16 continues the count-up operation. Then, when the memory update is completed, the decoder unit 13 detects the special code END, sends the information to the transfer control unit 14, and transfers control j? R14 performs a transfer operation of 11110H. In this case, since the address squid 1 output from the counter unit 16 is not affected by the data transfer 11-, the timing of the transferred data is not compromised, as described in Ti1i. Therefore, for example, screen refresh data will be displayed at the corresponding screen position.

On the other hand, on the computer side, the transfer control unit 14
By using M, the contents of the memory can be arbitrarily updated when necessary, regardless of whether the transfer operation is in progress or not, allowing more efficient memory use.

Effects of the Invention As described above, in the present invention, when the computer updates the contents of the memory, a special code is added before and after the changed data, and the transfer control unit updates the data by detecting the special code. Since the address counter section in the transfer control section is configured to continue counting up as usual during the 11- and lIf times during the transfer, and during the 11-time period during the transfer, the defective data being changed can be transferred to the outside. This has the effect of preventing this. Further, the timing of the transferred data will not be out of order when the transfer is restarted. Furthermore, it does not prohibit the computer from accessing the memory during data transfer, or prohibits the transfer control unit from accessing the memory when the computer updates the memory, allowing for more efficient memory use. It becomes seven.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing an example of insertion of change data and special codes in the above embodiment. Referring to the figure, 11"j) -t -':; De-1-der section, 12-register section, 13: Decoder section, 14: Transfer control section, +5: /< Transfer section, 16: Address counter section , 101: Digital data, MEN: Memory. Applicant: NEC Corporation Agent Patent attorney: Tosumune Sumita Figure 1, Figure 2L

Claims (1)

[Claims] In a common memory control system that includes a transfer control unit that transfers data stored in a memory connected to a computer to the outside asynchronously with the computer, the computer adds a special code before and after the data being changed. A message decoder section is provided to decode the data on the data bus and detect the special code, and the transfer control section stops or stops the data transfer operation according to the output signal of the message decoder section. A common memory control method featuring restart.