JP2581234B2 - Arithmetic unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic device, and more particularly to an arithmetic device that obtains a solution of a complicated arithmetic operation including a polynomial operation and a vector operation or a special code conversion.

[Conventional technology]

Conventional arithmetic devices replace the execution of complicated arithmetic operations including polynomial operations and vector operations or special code conversion operations with a pre-calculated operation result or code conversion in an external storage device for each operation process. A table in which a solution (hereinafter referred to as table data) is set and a table reference procedure (hereinafter referred to as a table program) indicating a procedure for referring to and executing the table are read and converted, or the table data and the table are read. The program and the program were stored in a non-rewritable mask ROM, and were directly mounted on an arithmetic unit.

[Problems to be solved by the invention]

In the conventional arithmetic device described above, when an external storage device is used, the access time and the waiting time are long,
There is a problem that the processing capacity of the main control unit is reduced.
In addition, when the data is stored in the mask ROM and mounted directly on the arithmetic unit, the prior evaluation period becomes longer because rewriting is not possible.
Moreover, there is a problem that it is not versatile.

An object of the present invention is to read out a table in which calculation results or table data are set from an external memory at the time of initial setting and a table program indicating a procedure to be executed by referring to the list and transfer the table program to a built-in memory, so that access time and time can be reduced. It is an object of the present invention to provide an arithmetic unit that can shorten the waiting time, can easily change table data and a table program, and can cope with various arithmetic operations and code conversions.

[Means for solving the problem]

The arithmetic unit of the present invention prepares a list in which a calculation result or a code conversion solution is set in advance in a storage device in place of execution of a complicated arithmetic operation including a polynomial operation and a vector operation or a special code conversion operation. In an arithmetic device for obtaining a solution of the arithmetic operation or code conversion by referring to the list, a list in which the calculation result or the solution of code conversion is set from an external memory provided externally via an external memory bus. A direct memory access controller for controlling reading and transferring a list reference procedure indicating a procedure for referring to and executing the list to a built-in memory, and a main control unit for controlling each unit in the apparatus; A list in which a plurality of calculation results or code conversion solutions are set, and a list reference procedure showing a procedure for referring to and executing the list. By storing in a built-in memory a list in which any operation result or code conversion solution is set at the time of initial setting and a table reference procedure showing a procedure for referring to and executing this list, any complicated In this configuration, a solution for arithmetic operation or special code conversion is obtained.

The arithmetic unit according to the present invention may include a shift register having a function of receiving serial data from an external line and outputting the data as parallel data to the external memory bus.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of one embodiment of the present invention.

An arithmetic unit 1 for performing arithmetic processing of packet data reads a main control unit 2 for controlling each unit in the arithmetic unit 1 and an arithmetic result or table data and a table program from an external memory 8 via an external memory bus 7. A direct memory access controller (hereinafter referred to as DMAC) 4 for controlling transfer to the internal memory 3 and an internal memory bus 5 for exchanging data between the main controller 2 and the internal memory 3
And a shift register 6 having a function of receiving serial data from the external line 10 and outputting the data as parallel data to the external memory bus 7. The external memory bus 7 temporarily stores data output from the arithmetic unit 1. The buffer 9 is connected.

 Next, the operation will be described.

When the arithmetic unit 1 is initialized, the main control unit 2
Is started, and control is performed so that the operation result or the table data and the table program are read from the external memory 8 via the external memory bus 7 and transferred to the internal memory 3. After the transfer is completed, this transfer control is not performed until initialization is performed again.

In this state, the shift register 6 receiving the serial data from the external line 10 outputs the serial data to the external memory bus 7 as parallel data.

 FIG. 2 is a data format diagram of the parallel data.

Parallel data is packet header 21 with byte numbers 1, 2, and 3.
And an error correction code (hereinafter referred to as FEC) of byte numbers 4 and 5 22
And a packet data section 23 having byte numbers 6, 7 to n.

The main control unit 2 receives the parallel data on the external memory bus 7, first decodes the packet header 21 and the FEC 22,
Check whether the packet header 21 is normal using EC22,
If abnormal, correct it to the correct value. All of these series of data conversion operations are executed by exchanging calculation results or table data and table programs with the internal memory 3 via the internal memory bus 5.

After the packet header 21 is correct or corrected to a correct value, the main control unit 2 transfers the packet header 21, the FEC 22, and the packet data unit 23 to the reception buffer 9 via the external memory bus 7.

When it is desired to use the parallel data FEC 22 as a mere error detection code, the processing starts from the initial setting, and from the external memory 8 via the external memory bus 7, the operation result for error detection code or table data and table program and Is read out and transferred to the built-in memory 3 to be executable.

〔The invention's effect〕

As described above, the present invention reads out a list in which the calculation result or the solution of the code conversion is set from the external memory at the time of the initial setting, and a list reference procedure indicating the procedure of referring to and executing the list, and reads the list into the internal memory. By the transfer, the access time and the waiting time can be reduced, the table data and the table program can be easily changed, and there is an effect that various arithmetic operations and code conversion can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a data format diagram of the parallel data. 1 arithmetic unit, 2 main control unit, 3 built-in memory,
4 Direct memory access controller (DMA
C), 5: internal memory bus, 6: shift register,
7 ... external memory bus, 8 ... external memory, 9 ... reception buffer, 21 ... packet header, 22 ... error correction code (FEC), 23 ... packet data section.

Claims (2)

(57) [Claims] 1. A list in which a calculation result or a code conversion solution is set in advance in a storage device instead of performing a complicated arithmetic operation including a polynomial operation and a vector operation or a special code conversion operation is prepared. In an arithmetic device for obtaining a solution of the arithmetic operation or code conversion by referring to a table, a list in which an operation result or a solution of code conversion is set from an externally provided external memory via an external memory bus and the list A direct memory access controller that controls reading and transferring a list reference procedure indicating a procedure to be performed by referring to a table to a built-in memory, and a main control unit that controls each unit in the apparatus; A list in which a plurality of operation results or code conversion solutions are set and a list reference procedure indicating a procedure for referring to and executing the list are stored. By transferring to the built-in memory a list in which any calculation result or solution for code conversion is set at the time of initial setting and a list reference procedure indicating the procedure for referring to and executing this list, any complicated arithmetic operation or An arithmetic unit for obtaining a special code conversion solution. 2. The arithmetic unit according to claim 1, further comprising a shift register having a function of receiving serial data from an external line and outputting the data as parallel data to said external memory bus.