JPS6361352A - Data transfer method for microprocessor system - Google Patents

Abstract

PURPOSE:To simplify the connection between memory units and to contrive to improve a data transferring speed by supplying respectively and independently the address of a transfer source and a transfer destination to a memory when transferring data between memory units. CONSTITUTION:When data are transferred from a memory 13 of a memory unit 17 to a memory 18 of a memory unit 22, the address of the transfer source is inputted to an AGC 14 and the address of the transfer destination is inputted to an AGU 19. Simultaneously, after the number of transferring data is inputted to counters 15 and 20 of a memory unit, the starting of the transfer is commanded to the memory unit. Next, the AGU 14 sends the address of the transferring data to the memory 3 and the memory 13 outputs the data designated by the address to a data line 23. On the other hand, the AGU 19 sends the accommodated address of the data to the memory 18 and the memory 18 accommodates the data on the data line 23 to the designated address.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for data transfer in a nine-microprocessor system with multiple memory units.

(Prior Art) Conventionally, when data is transferred between multiple memory units in a microprocessor, especially when the transfer is controlled at high speed by dedicated hardware without relying on the processor's program execution, the parts involved in memory data transfer are For example, it was common to have a groove bottom as shown in FIG.

That is, this is a microprocessor that first gives transfer control instructions.
(hereinafter abbreviated as MPU) 1, a memory unit 2 that stores transfer data, and a memory unit 3 to which the data is transferred are connected by address lines 4 and data lines 5, respectively, and data is transferred to these. A counter 6 that counts the number of data and an address generation N that generates the transfer source memory address.
Unit (hereinafter abbreviated as AGTJ) AGTJt7. AGU that generates the memory address of the transfer destination! 8. Said AGUt
A DMAC (Direct Memory) consists of a multiplexer 9 that switches address outputs of AGU 7 and AGU 8, a register 10 that temporarily holds transfer data, and a ninth decoder 11 that selects these registers, counters, etc.
y Address Controller below DMAC
It is constructed as if approximately the following DMA material was added.

However, in the conventional configuration as described above, it is not possible to output the transfer source address and the transfer destination address to the address line 4 at the same time. This method has the drawback that the data transfer speed is slow because it requires two transfer operations: storing the data in memory 2 to register 10 and transferring the contents of register 10 to memory 3 in the 9th transfer cycle. Ta.

OBJECTS OF THE INVENTION The present invention has been devised to obviate the disadvantages of conventional data transfer methods as described above and which simplifies connections between memory units and significantly increases transfer speeds. The purpose is to provide a data transfer method.

(Summary of the invention!') In order to achieve this object, the present invention has the following configuration.

That is, in order to transfer data between a plurality of memory units, each memory unit is provided with a memory address generation unit and a transfer number counter or a transfer end address determination unit, and each memory unit independently determines the data transfer source and transfer destination addresses. Therefore, prior to a transfer operation, an initial value is input from the microprocessor to each memory address generator and transfer number counter via the address line and data line, without using the address line thereafter. Furthermore, the data transfer operation is configured such that the number of transferred data is equal to the number of transfer cycles.

(Embodiments of the Invention) The present invention will be described in detail below based on illustrative embodiments.

FIG. 1 is a block diagram showing an embodiment of a memory data transfer section relating to a data transfer method in a microprocessor system of the present invention.

In the figure, 13 is a memory for storing data,
One memory unit 17 including an AGU 14 that gives a transfer source or destination address to the memory 1713, a transfer number counter 15, and a ninth address decoder 16 that selects either these counters 15 or the AGU 14. #Memory unit 17 and
Similarly, memory 18, AGU 19, counter 2
0 and an address decoder 21, connected to the memory unit 22 by a data line 23, and further provided with an MPU 24 for instructing transfer, and an address line is connected between the MPU 24 and each of the memory units 17 and 22. 25 and a data line 23.

When data is transferred from the memory 13 in the memory unit 17 to the memory 18 in the memory unit 22 using the memory data transfer section configured in this way, first, the MPU 24
inputs the initial address of the transfer source memory unit 17 to the AGL] 14 belonging to this via the address line 25 and data line 23, and inputs the initial address of the transfer destination memory unit 22 to the AGtJ19, and also inputs the number of transfer data. After inputting the data to the counters 15 and 20 of each memory unit, each memory unit is instructed to start a transfer operation.

Next, the AGU 14 in the memory unit 17 sends the address of the data to be transferred to the memory 13, and the memory 13 outputs the data content specified by the address to the data line 23, while the AGU 19 in the memory unit 22 stores the data. The address is sent to the memory 18, and the memory 18 stores the data on the data life 23 in the designated address area.

Furthermore, each time the above-described data transfer operation between memories is completed, the counters 15 and 2 in each memory unit 17.22 are
The value of 0 is decreased by 1, and the address output of each AGU 14, 19 is updated to a predetermined value, data is transferred one after another, and when the values of the counters 15 and 20 both become zero, the data transfer operation starts. end.

In this way, by providing the address generator and the number of data required for data transfer for each memory unit, it is possible to specify the transfer source memory address and the transfer destination memory address at the same time, and directly transfer data between memories. Moreover, since it is not necessary to use the address line except for initial address setting and transfer setting, high-speed data transfer is possible at twice the speed of the above-mentioned nine conventional methods.

The present invention may be modified as follows.

FIG. 3 is a block diagram showing an embodiment in which the memory unit 17 portion of FIG. 1 is modified, and in this modified embodiment, the memory unit 170 counter in FIG. A register 32 is provided, and a comparator 33 is added to compare the contents of the address register 32 and the output from the AGU 28.Other configurations and connections are the same as in FIG. be.

In the memory unit 26 configured in this way, the operation of the memory unit 17 in FIG. First, the final address is input into the register 32, and each time data is transferred, this value is compared with the output value from the AGU 28 by the comparator 33, and the data transfer is repeated until the two match.

In other words, the memory unit 17 in figure lr1 controls the end of transfer depending on the number of transferred data, and the memory unit 2 in figure 3
No. 6 is configured to control the end of transfer based on the final address of transfer, and the other functions are the same.

It will be obvious that not only the nine modified memory unit shown in FIG. 3 may be replaced with the memory unit 17 of FIG. 1, but also this memory unit may be used in place of the other memory unit 22.

In the above two or more examples, a description of the operation of the control lines related to data reading and writing will be omitted to simplify the explanation, but these operations are performed in the same manner as the conventional method shown in FIG. 82.

(Effects of the Invention) Since the present invention is configured and functions as described above, it is effective in simplifying the connection between memory units and increasing the data transfer speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory data transfer section related to the data transfer method in a microprocessor of the present invention, FIG. 2 is a configuration diagram of a conventional memory data transfer section, and FIG. 3 is a block diagram of the present invention. It is a block diagram showing a modification example of. 24・-・・・・・・MPU (Microprocessor unit)), 17,22.26・・・・・・
...Memory unit, 14,19.28・
・・・・・・・・・AGU (address generation N),
15.20・・・・・・Counter, 2
3.31... Data line. 25.30・・・・・・Address line. 32...Final address register. 33... Address comparator.

Claims (1)

[Scope of Claims] 1. In a method for transferring data between a plurality of memory units according to instructions from a microprocessor, each of the plurality of memory units is provided with a memory address generation unit and a counter. 1. A data transfer method in a processor system, characterized in that by simply inputting initial values to a generator and a counter via an address line and a data line, the use of the address line is made unnecessary thereafter. 2. An address register is provided in place of the counter, and a comparator is provided to compare the output of the address register with the output of the address generator, and the start address value is input to the address generator, and the final address value is input to the address counter. Data transfer in the processor system according to claim 1, wherein the comparator compares the start and final address values and generates addresses until they match. Method.