JPS63167939A - Emulator for microcomputer with built-in plural processors - Google Patents

Abstract

PURPOSE:To take a synchronization between each mode, and to switch the mode in the relation of master/slave, by providing a circuit for arbitrating a state detecting signal of each processor emulator, and switching an emulation mode to a debug mode by its output. CONSTITUTION:Processor emulators 1, 3 for a plural processor built-in type microcomputer are connected through an emulator control part 2 and an arbitrating circuit 16. Outputs of state detecting circuits 5a, 5b are inputted to the circuit 16, and its outputs 18a, 18b are inputted to the respective emulation control parts 7a, 7b. The circuit 16 takes AND of state detecting signals 17a, 17b and outputs it to the control parts 7a, 7b. Only in case when emulation parts 6a, 6b have become equal to a condition which has been set in advance to the circuits 5a, 5b, each emulator 1, 3 shifts to a debug mode. The emulator 3 can be switched singly to the debug mode in its own emulation state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an emulator for program development of a microcomputer in which a plurality of processors are integrated on one chip.

[Conventional technology]

Figure 4 shows an example of a conventional emulator for a microcomputer with multiple built-in microprocessors.The example in this figure is an example of a microcomputer with two built-in processors. (not shown) has a processor emulator 1.3. Furthermore, an emulator control section 2 is provided to control these processor emulators 1 and 3. The operation of this emulator will be explained.

I will only explain processor emulator 1, but 3
The same explanation applies to .

First, emulation of the target processor is performed by the emulation unit 6a.
The memory address is outputted from address bus 12a to memory 4a storing the program to be executed from a. The memory 4a sends data to the emulation control unit 7 via the bus 13a according to the input address.
Output to a. If this processor emulator is in emulation mode, this emulation control section outputs the data from the bus 13a as it is to the emulation section 6a via the bus 14a. The data to be stored in this memory is written in advance by the emulator control unit 2 via the bus 9a. The means for shifting the processor emulator 1 from the emulation mode to the debug mode in which the internal state of the emulation section 6a can be checked and changed will be described below.

Note that such confirmation changes cannot be made in emulation mode. Here, we will consider a case where the mode is shifted when the above-mentioned address outputted from the emulation section 6a reaches a certain value as a condition for shifting the mode. First, data that is a condition for migration is set in the state detection circuit 5a from the emulator control section 2 through the bus 10a. The state detection circuit 5a determines whether the address output from the address bus 12a during emulation is a preset value, and if they match, outputs a signal to that effect to the emulation control section 7a through lla. If the emulation control unit 7a determines that the mode should be changed based on this signal, it stops inputting data from the memory 4a and outputting it to the emulation unit 6a, and instead outputs debugging data sent from the emulator control unit 2 through the bus 8a. do. Note that this data (program) is for checking the internal state. With this debugging data, the emulation section 6a sends the internal state to the emulator control section 2 via the bus 15a, and the emulator control section 2 can confirm the internal state of the emulation section 6a. Transition from debug mode to emulation mode is performed by directly controlling the emulation control unit from the status detection circuit 7a.Evaluation of the program stored in the memory 4a is normally performed by switching between emulation mode and debug mode to check the internal state. I will do it while doing it.

These things are the same for the 3rd processor and emulator in this example. In this way, in the prior art, the conditions for changing the mode of each processor emulator are limited to the conditions of each processor emulator itself.

[Problem that the invention seeks to solve]

In the conventional technology described above, the conditions for switching each processor emulator from emulation mode to debug mode are limited to the emulation state of each processor. For this reason, there is a drawback that synchronized switching between multiple processor emulators is not possible. For example, in the example of the prior art shown in FIG. 4, it was not possible to switch the states of processor emulator 1 and processor emulator 3 when a certain condition was reached. In order to solve the problems of the prior art, the signal from the state detection circuit 3 in the prior art example is not directly input to the emulation control unit, but instead the signal from the state detection circuit of each processor emulator is input. It has an arbitration circuit that arbitrates.

In contrast to the conventional emulator for a microcomputer with built-in multiple processors, the present invention provides a circuit that mediates the state detection signals of each processor emulator, and switches the mode of each processor emulator using the output signal of this circuit. It has original content that makes it possible.

〔Example〕

The present invention will be explained using the drawings. FIG. 1 is a block diagram of an emulator for a microcomputer with built-in multiple processors according to the present invention. Although it is basically the same as the prior art shown in FIG. 4, the signal from the state detection circuit 5a is not directly input to the emulation control section 7a,
The only difference is that the output signal 18a from the arbitration circuit 16 is input to the arbitration circuit 16 through the emulation section 6a, and the output signal 18a from the arbitration circuit 16 is input to the emulation control section 7a.
The functions of the state detection circuit 5a, memory 4a, and emulation control unit 7a are the same as those in the prior art, and the same applies to the processor emulator 3. The arbitration circuit 16 receives state detection signals 17a and 17b from the state detection circuits 5a and 5b of the processor emulators 1 and 3, arbitrates these signals, and outputs the results to the respective emulation control sections 7a and 7b.

Next, an example of this arbitration circuit will be shown, and FIGS. 2 and 3 are diagrams showing examples of the arbitration circuit. FIG. 2 is a circuit diagram showing an embodiment of the arbitration circuit. The state detection signals of the respective processor emulators sent from 17a and 17b are simply ANDed using an AND gate, and this output is sent to 18.
a, 18b through the respective emulation control units 7a.

Output to 7b. In this embodiment, each processor emulator shifts from the emulation mode to the debug mode only when the emulation units 6a and 6b of the processor emulator meet the conditions set in advance in the respective state detection circuits 5a and 5b. become.

FIG. 3 is a circuit diagram showing a second example embodiment of the arbitration circuit. Here, the signal outputted to one processor emulator through the signal line 18a is the AND signal of the outputs from the state detection circuits from the respective processor emulators, as in the case of FIG. The signal output to the processor emulator 1 of 3 through 18b is the state detection signal of 17b sent back as is. However, the processor emulator No. 3 can switch from emulation mode to debug mode in its own emulation state. The mode of processor emulator No. 1 is switched only when the preset conditions for both processor emulators No. 1 and No. 3 are met.

〔Effect of the invention〕

As explained above, in order to switch the emulation mode of the processor emulators constituting the emulator of a microcomputer that integrates multiple processors, an arbitration circuit is provided to arbitrate the state detection signals of each processor emulator, and the output of this arbitration circuit is By making it possible to switch emulation mode to debug mode, the following effects can be achieved. First, conventionally, the mode of each processor emulator was switched only depending on the state of the emulation section of each processor emulator, but with the present invention, the mode of each processor emulator can be switched based on the synchronization between processor emulators and the master/slave relationship. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an emulator for a microcomputer with built-in multiple processors according to the present invention, FIGS. 2 and 3 are diagrams showing embodiments of an arbitration circuit, and FIG. 4 is a block diagram of a conventional emulator. In the figure, 1 is a processor emulator, 2 is an emulator control unit, 3 is a processor emulator 4a, 4b is a program storage memory, and 5a. 5b is a state detection circuit, 6a and 6b are emulation sections, 7a and 7b are emulation control sections, 16 is an arbitration circuit, and 20.21 is an AND gate.

Claims (1)

[Claims] In a microcomputer emulator in which a plurality of processors are integrated on one chip, the emulator includes a processor emulator that performs emulation for each of the integrated processors, an emulator control section that controls the plurality of processor emulators, and each of the above-mentioned processors. an arbitration circuit that receives a state detection signal indicating an emulation state from a processor emulator and outputs an arbitration signal to each of the processor emulators, and each processor emulator receives the emulation state of the processor from the emulator control unit. and an arbitration circuit that receives the respective state detection signals as input, arbitrates these signals, and outputs the signals to each processor emulator. An emulator for a microcomputer with a built-in multiple processors, comprising: an emulation control signal having means for switching the emulator from emulation mode to debug mode.