KR940001631A - Main Processing Module Control Circuit of Electronic Switch - Google Patents

Abstract

According to the present invention, the main processing module of the electronic switching system including the main processor and the internal memory is matched with the system bus and the redundant channel, and the coprocessor and the redundant counterpart processor on the main processor and the system bus are external to the internal memory and system bus. The present invention relates to a control circuit for arbitrating an access operation when accessing a memory and a counterpart memory through a duplex channel, and in particular, an all-electronic main exchange module for controlling an access operation when a plurality of processors simultaneously access a plurality of memories. It relates to a control circuit.

According to the present invention, in the main processing module of the electronic switching system matched to the system bus and the redundant channel, the plurality of accessor request signals for the respective processors in the main processor and the coprocessor and the redundant processing module on the system bus are controlled. It is possible to provide a main processing module control circuit of an all-electronic exchange that allows access operations by different processors to be performed evenly.

Description

Main Processing Module Control Circuit of Electronic Switch

Since this is an open matter, no full text was included.

3 is a block diagram of a system to which a main processing module control circuit of an all-electronic exchange according to the present invention is applied;

Figure 4 is a block circuit diagram showing the configuration of the main processing module control circuit according to the present invention.

Claims (4)

When access is requested from the main processor, the system bus, and the redundant channel, the decoder unit A generates an access request signal corresponding to each other, and a plurality of access request signals input from the decoder unit A in the order of processing. Selecting one by one to generate a selection signal corresponding to each access request signal, and an arbitration circuit 44 for generating a corresponding operation request signal according to the location of the access requested memory, and generates a signal for memory control And an internal memory control circuit 48 for executing access to internal memory according to the input operation request signal 57 and generating an operation completion signal 510 after the access is completed, and an input operation request signal 58. System bus that executes access to the external memory on the system bus and generates an operation completion signal 510 after the access is completed. Outputs an access request signal to the other main processing module via the duplex channel according to the sum circuit 49 and the input operation request signal 59, and generates an operation completion signal 517 after the corresponding access is completed. The dual channel matching circuit 57 and the arbitration circuit 44 monitor the selection of the selection signal for the main processor, the system bus and the redundant channel, and the internal memory control circuit 48 when the selection signal is input. (B) receiving an operation completion signal 510 from the system bus matching circuit 49 or the redundant channel matching circuit 57, and outputting a response signal to the corresponding processor; Control circuit of main processing module of exchange. The main processor decoder (41) according to claim 1, wherein the decoder (A) outputs an access request signal (51) corresponding to an access request from the main processor. The system bus decoder 42 outputs an access request signal 52 corresponding to the access request from the system service, and the redundant channel decoder outputs an access request signal 53 corresponding to the access request from the redundant channel. 43. A main processing module control circuit for an all-electronic exchange comprising: 43). 2. The circuit of claim 1, wherein the response circuit portion B includes a main processor response circuit 45, a system-bis response circuit 46, and a redundant channel response circuit 47, and the response circuits 45, 46, 47 respectively. Main processing module control circuit of an electronic switch, characterized in that to output a response signal to each processor corresponding thereto. The electronic circuit of claim 1, wherein the arbitration circuit 44 arbitrates the access request signals from the system bus and the duplex channel of the main processor so that the access request of each processor can be evenly selected and executed. Control circuit of main processing module of exchange. ※ Note: The disclosure is based on the initial application.