KR19990062330A - Interrupt Control in Multi-Processor Systems - Google Patents

Abstract

The present invention provides a multi-processor for enabling separate interrupt control between processors by designating interrupt data allocated to each slave processor while a plurality of slave processors are implemented on-board with respect to a single master processor. An interrupt control apparatus for a processor system.

According to the present invention, in a multi-processor system in which at least two or more slave processors (130,140) are implemented on-board for a single master processor (100), from the master processor (100) to the slave processors (130,140). Interrupt control logic for generating an interrupt signal for the slave processor (130; 140) of the interrupt target based on the DPRAM (Dual Port RAM) 110 in which the interrupt data is recorded and the interrupt data recorded in the DPRAM 110. And an interrupt area for recording interrupt data uniquely allocated to the slave processors 130 and 140, and an interrupt of each slave processor 130 and 140 for the interrupt area. Data is intended to be recorded by the last address or (final address-1).

Description

Interrupt Control in Multi-Processor Systems

The present invention relates to an interrupt control apparatus of a multi-processor system, and more particularly, to a plurality of slave processors through a global memory in a multi-processor system having at least a single master processor and a plurality of slave processors. An interrupt control apparatus of a multi-processor system for enabling interrupt control for the present invention.

As is well known, in the case of a system which is designed to process a large amount of audio / video data or text information data at high speed and exchange it with an external peripheral device, a plurality of master processors operating under the control of the master processor and at least one master processor may be used. The slave processor is implemented in the form of a so-called 'multi-processor system'.

Thus, such a multi-processor system typically branches under the control of the master processor by temporarily suspending the service routine of the particular slave processor from the master processor while the particular slave processor is performing data processing based on a programmatic service routine. An interrupt scheme is set up for requesting to perform a routine service routine or for requesting to perform a branched service routine by temporarily suspending the service routine of the master processor from a specific slave processor.

1 is a block diagram illustrating an interrupt control apparatus of a multi-processor system according to an exemplary embodiment. In the figure, reference numeral 10 denotes a processor (e.g., a slave processor) configured in a multi-processor system and assumed to be an interrupt target, and 20 is interposed between the processor 10 and a plurality of interrupt sources (not shown). And an interrupt arbitration section for delivering an interrupt request from the interrupt source to the processor 10, the interrupt arbitration section 20 having a latch circuit 30 and a three-state for storing the state of each interrupt source. The tri-state buffer 40 and the interrupt signals INT1 to INT8 from each interrupt source are connected to the input terminal, and the result of logical AND processing of the interrupt signals INT1 to INT8 is outputted to the interrupt terminal of the processor 10. And an AND gate 50 to be applied.

According to the interrupt control process of the conventional multi-processor system realized by such a configuration, the interrupt source of the entire interrupt source 20 is interposed between the interrupt target processor 10 and the plurality of interrupt sources. If no interrupt is generated from the interrupt signal (INT1-INT8), the interrupt signal (INT1-INT8) is maintained at a high level, and the state data of each interrupt source is based on the external clock signal (CLK). It is stored in 40.

In this state, the AND gate 50 obtains a high level output from the logical AND result of the normal level (that is, the high level) of each interrupt signal INT1-INT8, so that the interrupt terminal of the master processor 10 ( ), And thus, the master processor 10 executes a normal operation.

When an interrupt signal is generated from any one of a plurality of interrupt sources, the state of each interrupt source is stored in the latch circuit 30 and the tri-state buffer 40, and low from the AND gate 50. A level signal is output so that the interrupt terminal of the interrupt target processor 10 ( ), The interrupt target processor 10 recognizes a state in which an interrupt request from an interrupt source is generated. Then, the processor 10 applies the chip select signal CS * and the write / read control signal Rx / Wx to the latch circuit 30 and the tri-state buffer 40 to provide status data of each interrupt source. It reads and determines whether the interrupt request is its own interrupt and its interrupt source, and if it is its own interrupt, it performs the corresponding interrupt function.

By the way, according to the interrupt control method shown in FIG. 1, when an interrupt request is generated from any one of the interrupt sources in a state in which a plurality of interrupt sources (slave processors) are connected to the processor 10 as the interrupt target. The processor 10 must read the state data of each interrupt source stored in the latch circuit 30 and the buffer 40 after recognizing the interrupt request through the AND gate 50, and then the master processor 10 must read the interrupt data. The interrupt source that requested the interrupt can be determined. In addition, whenever an interrupt request is generated from at least one interrupt source among a plurality of interrupt sources, the processor 10 reads the state data of the latch circuit 30 and the tri-state buffer 40 to determine the state of each interrupt source. It is necessary to perform the checking process repeatedly, so that the processor 10 not only increases the software burden for determining whether an interrupt request is generated, but also increases the power consumption and machine cycles in the interrupt service routine. There is a disadvantage that the cycle is increased in consumption.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances of the prior art, and allows a plurality of processors configured in a multi-processor system to share the same interrupt rank, and to determine in advance a processor that generates an interrupt so that the interrupt signal is separated between processors. It is an object of the present invention to provide an interrupt control apparatus of a multi-processor system, which enables real-time recognition of the processor that generated the interrupt.

In order to achieve the above object, according to a preferred embodiment of the present invention, in a multi-processor system in which at least two or more slave processors are implemented on-board for a single master processor, the master processor and the two or more slaves. The processor shares the address / data / control bus under the control of the global bus control logic, and the DPRAM (Dual Port RAM) in which the interrupt data for the slave processor is recorded from the master processor, and the interrupt data recorded in the DPRAM. An interrupt control apparatus for a multi-processor system configured to include an interrupt control logic for generating an interrupt signal for the slave processor to be interrupted is provided.

Preferably, the DPRAM is allocated an interrupt area in which interrupt data uniquely allocated to the slave processor is recorded, and the interrupt data of each slave processor for the interrupt area is determined by a final address or (final address-1). Record is specified.

In addition, according to the present invention, the interrupt control logic is configured to include an interrupt separation logic for separately generating an interrupt signal for a slave processor determined by the interrupt data and the slave processor determined by the interrupt data.

According to the interrupt control apparatus of a multi-processor system according to the present invention having the above configuration, in a multi-processor system in which a plurality of slave processors are implemented on-board for a single master processor, the master processor is an interrupt target processor. When the unique interrupt data allocated to is written to the interrupt area of the DPRAM, the interrupt signal for the interrupt processor of the interrupt target is generated in real time from the interrupt control logic based on the interrupt data, and is applied to the corresponding slave processor. To act.

1 is a block diagram illustrating an interrupt control apparatus of a multi-processor system according to an exemplary embodiment of the present invention;

2 is a block diagram illustrating an interrupt control apparatus of a multi-processor system according to an exemplary embodiment of the present invention;

3 is a diagram showing an example of the configuration of the interrupt control logic shown in FIG. 2;

4 is a timing chart illustrating an interrupt control apparatus of a multi-processor system according to the present invention.

* Description of the symbols for the main parts of the drawings *

10: processor, 30: latch circuit,

40: 3-state buffer, 50: AND gate,

100: master processor, 120: interrupt control logic,

110: Dual Port RAM (DPRAM), 130,140: Slave Processor,

150: global bus control logic.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

2 is a block diagram illustrating an interrupt control apparatus of a multi-processor system according to an exemplary embodiment of the present invention.

In the figure, reference numeral 100 denotes a master processor that is responsible for main control functions in a multi-processor system. According to the present invention, the master processor 100 is based on unique interrupt data allocated to at least two slave processors. Specify the target slave processor. Reference numeral 110 denotes a DPRAM (Dual Port RAM) shared by the master processor 100 and a later-described slave processor that is connected in signal, and according to the present invention, a predetermined number of the DPRAM 110 according to the present invention. The unique ID data of the processor whose area is designated as the interrupt target among each slave processor is allocated as the interrupt area in which the area is recorded as the interrupt data.

In FIG. 2, reference numeral 120 denotes a slave processor 130 and 140 separately generated by the master processor 100 to generate an interrupt signal from the master processor 100 and corresponding slave processor. An interrupt control logic for interrupt control 130 and / or 140).

In addition, 150 denotes a global bus control logic for controlling the operation of the master processor 100 and the slave processors 130 and 140 to exchange messages via the DPRAM 110.

Here, according to the present invention, when arbitrary data is written to the final address area of the DPRAM 110, an interrupt is generated from the left to the right, whereas the random address is located in the area of the (final address-1) of the DPRAM 110. It is assumed that an interrupt is generated from right to left in the case of recording data, and accordingly, an interrupt signal can be generated separately using the write data in the case of recording data in the interrupt area of the DPRAM 110. Done.

In addition, according to the present invention, the DPRAM 110, the interrupt control logic 120, the first to nth processors (i.e., the slave processor) and the global bus control logic 150 are on-board. The first through nth processors 130 and 140 are assumed to access the DPRAM 110 by sharing an address bus, a data bus, and a control bus under the control of the global bus control logic 150.

FIG. 3 is a diagram showing an example of the configuration of the interrupt control logic 120. The interrupt control logic 120 is provided from the master processor 100 and stored in the DPRAM 110 and recorded / stored with data DT. Read control signal And a register 122 in which the chip select signal CS * is temporarily stored, data DT stored in the register 122, and an active-low level interrupt signal recorded in a predetermined area of the DPRAM 110. It is configured to include an interrupt separation logic 124 for separately generating the interrupt signal (Int1-Int8) for the plurality of slave processors (130,140) based on.

Next, the operation of the interrupt control apparatus of the multi-processor system according to the present invention having the above-described configuration will be described with reference to the timing chart shown in FIG.

First, when the master processor 100 wants to request an interrupt from, for example, the first processor 130 among the plurality of slave processors 130 and 140, the master processor 100 responds to the address signal AD (see FIG. 4). ID data (e.g., 00h) allocated to the first processor 130 is recorded as interrupt data in a predetermined area (i.e., an interrupt area) of the DPRAM 110 that can be designated by the program.

Then, the register 122 of the interrupt control logic 120 writes / writes a control signal to the DPRAM 110. And data DT from the master processor 100 are temporarily stored based on the chip select signal CS * (see FIG. 4) and then applied to the interrupt isolation logic 124, and the interrupt isolation logic 124. FIG. ) Is interrupt data provided in the interrupt area of the DPRAM 110. Generates an interrupt signal (eg, Int1; see FIG. 4) to the first processor 130 based on the first processor 130 and generates an interrupt signal to the first processor 130. Will enter.

In contrast, when the master processor 100 makes an interrupt request to the n-th processor 140, the master processor 100 transmits the n-th to the interrupt area of the DPRAM 110 similarly to the above-described process. When the interrupt data allocated to the processor 140 of the processor 140 is recorded, the interrupt control logic 120 generates an interrupt signal Intn (see FIG. 4) for the nth processor 140 based on the interrupt data. To be applied to the corresponding nth processor 140.

Therefore, according to the present invention, when the interrupt data recorded in the interrupt area of the DPRAM 110 is set to the ID data assigned at the time of design for the slave processor configured on the on-board, the interrupt target processor is executed in real time. It is possible to generate a separate interrupt signal. In addition, the number of processors that can be connected is determined based on the number of bits of the data DT used to generate interrupt signals for a plurality of processors. For example, in the case of 8 bits, a maximum of 256 processors may be connected.

As described above, according to the interrupt control apparatus of the multi-processor system according to the present invention, the real time of the interrupt signal for the corresponding processor based on the interrupt data uniquely assigned to the plurality of processors configured in the multi-processor system. It is possible to generate a separate and separate process between processors, thereby reducing the program burden for determining the processor to be interrupted and shortening the machine cycle in the interrupt service routine.

Claims (3)

In a multi-processor system in which at least two slave processors (130, 140) are implemented on-board for a single master processor (100), The master processor 100 and the two or more slave processors 130 and 140 share an address / data / control bus under the control of the global bus control logic 150, Dual port RAM (DPRAM) 110 in which interrupt data for the slave processors 130 and 140 are recorded from the master processor 100, and An interrupt control logic (120) for generating an interrupt signal for the slave processor (130; 140) of the interrupt target based on the interrupt data recorded in the DPRAM (110). Interrupt Control. The method of claim 1, wherein the DPRAM 110 is allocated an interrupt area for recording interrupt data uniquely allocated to the slave processors (130, 140), the interrupt data of each slave processor (130, 140) for the interrupt area is An interrupt control apparatus for a multi-processor system, characterized in that it is designated by the last address or (final address-1). The interrupt control logic 120 of claim 1, wherein the interrupt control logic 120 separately generates an interrupt signal for the processor 122 and the slave processor 130 and 140, which are determined by the interrupt data, which are stored by the interrupt data. Interrupt control logic of the multi-processor system, characterized in that it comprises an interrupt separation logic (124).