JP3394834B2 - Debugging method for devices that make up a multiprocessor system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debugging system for devices constituting a multiprocessor system.

Various systems have come to be used by multiprocessors. For example, when developing a large-scale system such as a switching system, a large number of devices each having a different function are separately developed, and each system is developed. I debug and test individually. For this reason, the reliability varies from device to device, and when the entire system is put together, it takes a lot of time and effort to check various devices while connected to a host device that controls the entire system. The improvement is desired.

[0003]

2. Description of the Related Art FIG. 6 is an explanatory view of a conventional example. A. of FIG. Shows the configuration of a general multiprocessor system. In the figure, 60 is a host device for controlling the entire system, 6
1 is various devices each having an independent function (devices 1 to 1
62 is a system bus that connects each device 61 and the host device 60, and is a host device 6 of the control system.
0 and each device 61 are respectively provided with microprocessors, each function is executed by a program, and each device 61 receives a command from the host device 60 and performs a control operation.

As an example of this system, there is, for example, a switching system, and as each device 61, a line control device, a signal device, an STM (Synchronous Transfer Mode) switch,
There are a large number of devices, each having a different function, such as a packet switching switch.

When the multiprocessor system is composed of various kinds of devices having different functions, when developing the system, individual devices are developed and debugging is performed for each device.

FIG. 6B. A conventional function confirmation method is shown in Fig. 1, and in order to debug each device 61, a debug interface 63 having an individual configuration corresponding to the type of each device 61 is created, and a test device 64 (PC Or workstation)
The function is confirmed by sending a command or data from the test device 64 to the device 61 to check the operation of the target device 61.

Further, since it is not possible to confirm whether or not the system 61 operates normally only by performing a unit test of the device 61, the respective devices and the host device 60 of the control system are designated as A.A in FIG.
After the entire system is connected as described above, debugging is performed to confirm the function of each device and the function of the entire system.

[0008]

Even if the function of the device is confirmed by using the above-mentioned individual interface, the interface is different from the interface with the host device provided in the actual system, so that the operability is poor and the device is used for debugging. Most of the items checked from the interface had to be rechecked by connecting an actual device.

When confirming the function of each device in a state where it is connected to the host device, since a large number of various devices are provided, it is necessary to debug each device 61 from one host device 60 in order. Took a great deal of time. Therefore, a method of using a large number of upper devices can be considered, but it is difficult to increase the number of upper devices because it is expensive, so it takes a long time to check the functions of all the devices.

Some devices operate in cooperation with other related devices. However, when other devices are developed in parallel at the same time, it is possible to connect the two to check the function. There was a problem that I could not. This is also a problem that occurs when developing higher-level equipment and equipment in parallel.

The present invention is an apparatus constituting a multiprocessor system which enables each apparatus constituting the multiprocessor system to perform function confirmation from the same external apparatus for apparatuses having different functions without the presence of a host apparatus.
The purpose is to provide a debugging method of.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is a device provided as a lower device with respect to the upper device 4 and having a processor and a unique function, 2 is a common unit having the same configuration in each device, and 2a is an interface with the upper device Upper device interface unit, 2b is a debug interface unit for interfacing with a device to be debugged, 3 is an individual unit having a configuration for executing a function peculiar to each device, 4 is an upper unit for controlling the entire system of the multiprocessor system Device, 4a
Is a hardware interface by a bus between the host device and each device, 5 is a processing device such as a personal computer for debugging, 5a
Is a hard interface between the device 1 and the processing device 5. Reference numeral 3a is a logical interface that serves as an interface between the common unit 2 and the individual unit 3. Note that Fig. 1
Although only one device 1 is shown in FIG. 1, a large number of devices 1 (not shown) constituting a multiprocessor system are arranged.

The present invention provides a plurality of devices having various functions,
It is composed of a common unit having a common configuration for each device and an individual unit having a configuration for executing individual functions corresponding to each device.
The common unit is provided with an interface with a higher-level device and an interface with a device for debugging, and each interface and an individual unit are connected by a logical interface.

[0014]

In FIG. 1, the common unit 2 of the device 1 has the same configuration as the other devices not shown in the figure, the upper device interface unit 2a therein has an interface function corresponding to the upper device, and the debug interface unit 2b processes. Device 5
Equipped with an interface function corresponding to. By this,
The common unit 2 absorbs the difference in the hardware interface based on the difference between the host device 4 and the processing device 5. The debug interface unit 2b can achieve its purpose if it can perform low-speed data transfer.
a has a function of performing high-speed operation when the system is configured and operated.

The format of commands and data from the host device 4 is common to various devices, and the host device interface unit 2a of the common unit 2 discriminates them as data and commands. In addition, each processing device 5
Commands and data from the device to the device 1 are also sent in a format common to various devices, and the debug interface unit 2 of the common unit
In b, it is determined as the same data and command as the host device interface section 2a. In this way, the difference in hardware control between the host device 4 and the processing device 5 is absorbed by the two interfaces.

The upper device interface section 2a and the debug interface section 2b can be treated as logically similar to the individual section 3, and the interface between them is called the logical interface 3a.

An application program provided in the individual unit 3 is debugged from the processing unit 5 via the debug interface unit 2b, and an application program confirmed to have no error is processed from the processing unit 5 to the individual unit 3 of the unit 1. Can be downloaded to.

[0018]

FIG. 2 is a hardware configuration diagram of an embodiment of a multiprocessor system constituent device.

In FIG. 2, 10 to 12 are 1 in FIG.
Each of the hardware parts corresponding to 3 to 10, 10 is a component device, 11 is a hardware common part, 12 is a hardware individual part, and the hardware individual part 12 is different hardware corresponding to the type of each component device 10, For example, in the case of an exchange system, a signal device and various switch devices are provided.

The common hardware unit 11 is used for various constituent devices 10
Is a microprocessor (denoted by μP), and 111 is a SIO (serial input / output) provided as a debug interface. Specifically, a well-known RS232C interface is used for debugging. It is connected with the personal computer etc. 112 is a PIC (processor interface
Controller), 113 is DMAC (Direct Memorry A)
ccess Controller: DMA control unit), 114 is a RAM in which data for performing processing in the common unit is held, 1
15 is an EPR in which fixed data and programs are stored
OM and 116 are EEPROMs in which modifiable data and programs are stored, 117 is a BIC (bus interface controller), and 118 is a bus of a common unit. G1 is a gate between the common part 2 and the individual part 3, and G2 is B
The gate connects the IC 117 and the bus 118 of the microprocessor.

FIG. 3 is a block diagram of the firmware of the embodiment of the multiprocessor system constituent device. FIG. 3 shows the firmware (referred to as firmware) of the common part and the individual part, and in FIG. 2 shows the same constitutional device as 10 and 11a is a common part of the farm, 12a
Is an individual firmware unit, and the individual firmware unit 12a is provided with its own firmware corresponding to the type of the constituent device 10, and the firmware is stored in an EEPROM (not shown).

The firmware common section 11a is a firmware common to various constituent devices 10, 11b is an OS and system call of the microprocessor 110, 11c is a debug common interface for processing an interface with a processing device for debugging, Reference numeral 11d is a system common interface that processes an interface with a higher-level device, 11e is a debug common interface 11c and a system common interface 11d, and a firm individual unit 1
This is a hardware common part control / individual part interface 11e for performing interface processing with 2a.

All the firmware 11b to 11e in the firmware common unit 11a is housed in the EEPROM 116 in the hardware common unit 11 shown in FIG. 2, and the microprocessor 110 executes program control.

In the case of debugging, from a personal computer (or workstation) or the like which conducts an external test, for example, by a low speed debug interface of RS232C,
When commands and data are transmitted in the form of serial signals in a fixed format, SI of the hardware common unit 11 is controlled by the debug common interface 11c of the firmware common unit 11a.
It is received at O111. This is processed as parallel data by the PIC 112, and the extracted commands and data are RA
It is stored in M114.

Further, the commands and data stored in the RAM 114 are passed to the firm individual unit 12a under the control of the hardware common unit control / individual unit interface 11e. At this time, the firm individual unit 12a receives a command and data as in the case of transfer from a normal host device, and executes the commanded function according to the data. The execution result and the state in the hardware individual unit 12 are transferred to the RAM 114 of the hardware common unit 11 via the reverse path under the control of the hardware common unit control / individual unit interface 11e according to the command, and further, in the debug common interface 11c. PIC11 by control
2, output to a personal computer or the like for testing via the SIO 111.

When the host device controls the constituent device 10 from the system bus interface, the BIC 117 is driven and the microprocessor 110 controls the gate G2 to be turned on. As a result, the system common interface 1
1d is driven, and its control enables mutual data transfer with the host device. When commands and data from the host device are sent at high speed in a format by the host device under the control of the system common interface 11d, the contents of the commands and data are stored in the RAM 114, and then the hardware common part control / individual part interface. It is passed to the individual farm unit 12a by the control of 11e (gate G1.
Via the gate G2). This is received under the control of the firm individual unit 12a, and the hardware individual unit 12 executes the unique function of the constituent device 10.

The data requested by the higher-level device is sent through the reverse path (the individual hardware unit 12 and the RAM 11 of the common hardware unit 11).
4 write, read from RAM 114, BIC11
7, route to the system bus interface).

In this way, the hardware and firmware of the common part are basically made common, and the difference in hardware control between the high-performance system bus interface and the inexpensive debug interface is absorbed by the firmware of the common part. There can be no difference in the interface (logical interface) with the individual parts.

Further, the firmware common part 11a and the firmware individual part 12a can all be housed in the EEPROM, and the firmware common part 11a is stored in the EEPROM 116 of FIG.
Stored in.

As a result of debugging the firmware individual section 12a via the debug interface of an external personal computer or the like, when the latest application program (firmware of the individual section) in which an error is corrected is obtained, the application program is configured from the personal computer or the like. 1
Farm individual unit 1 via 0 debug interface
It can be directly downloaded to the EEPROM of 2a, which eliminates the conventional work of removing the EPOM containing the firmware from the package and replacing it with the EPROM storing a new application.

FIG. 4 shows an example of the configuration when applied to an exchange system. This exchange system can be configured as a public network exchange system or a private network exchange system. In the figure, 1-1 to 1-n are a line control device, a signaling device, ... An ATM switch, respectively. , STM switches, which correspond to the device 1 of FIG. 1 and various constituent devices 10 shown in FIGS. 2 and 3. 2 is a common part, 3 is an individual part, 4
Is a host device for controlling the entire system, 4a is a system bus, and 5-1 to 5-n are personal computers for debugging.

As shown in FIGS. 1 to 3, each of the devices 1-1 to 1-n has a common part 2 having a common structure to each device and an individual part having a different structure to each device. 3 and 3. Each of the devices 1-1 to 1-1n was developed in parallel, and a personal computer 5-1 is provided for each device.
It is possible to perform debugging independently from .about.5-n. That is, the same commands and data as those from the higher-level device 4 are supplied from the personal computer, and debugging of the individual unit 3 is performed via the debug interface provided in the common unit 2 of each of the devices 1-1 to 1-1n. This is performed by the configuration described with reference to FIGS. 2 and 3 above.

In this way, even when the hardware and programs of the higher-level device 4 of the control system are incomplete or when the number of higher-level devices of the control system is insufficient, there is almost no difference from the presence of these devices. Development of multiple devices can be done in parallel, greatly reducing development time and costs.

FIG. 5 shows a personal computer for debugging as a LAN.
It is a configuration example in which they are mutually connected by. In FIG. 5, 1-1
1 to n, 2 to 4 correspond to respective devices having the same reference numerals in FIG. 4, 5-1 to 5-n are personal computers or workstations (indicated by WS), and 6 is a plurality of personal computers or WS. A LAN (including a case of connecting with a communication line) 7 is a personal computer or a workstation provided in a place different from other personal computers or workstations (hereinafter referred to as personal computers, etc.) 5-1 to 5-n. .

In this configuration, each device 1-1, which is a device,
Each personal computer or WS5-1 to 5-n connected to 1-n
In contrast, it is possible to access a PC or WS 7 installed at a remote place via the LAN 6 and execute debugging. Also in this case, it is possible to perform debugging even when the host device 4 of the control system is in an undeveloped state.

In both of the configurations shown in FIGS. 4 and 5, the hardware and software of the common section are shared at the time when the host device of the control system and each device are actually connected. The whole system can be operated.

[0037]

According to the present invention, when a multiprocessor system is developed, a plurality of devices can be developed in parallel regardless of the presence or absence of an actual opposite device (upper device to the device or other related device). Can be realized. In addition, the debug environment and the file creation (firmware creation) environment can be integrated by a single personal computer or workstation, so device development can be realized at low cost and in a short period of time.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a hardware configuration diagram of an embodiment of a multiprocessor system configuration device.

FIG. 3 is a firmware configuration diagram of an embodiment of a multiprocessor system configuration device.

FIG. 4 is a configuration example when applied to an exchange system.

FIG. 5 is a configuration example in which personal computers and the like for debugging are connected to each other via a LAN.

FIG. 6 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1 device 2 common department 2a Host device interface section 2b Debug interface section 3 individual departments 3a Logical interface 4 Host device or other device 4a Hardware interface with upper device 5 Processing equipment such as personal computers 5a Hardware interface with processor

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-223046 (JP, A) JP-A-6-28215 (JP, A) JP-A-6-325008 (JP, A) JP-A-3- 4338 (JP, A) JP-A-5-20120 (JP, A) Actual development 4-20144 (JP, U) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 11 / 28-11 / 34 G06F 15/177

Claims (2)

(57) [Claims] 1. In a debugging method of a device constituting a multiprocessor system composed of a host device and a plurality of various devices, the host device controlling the whole and the device connected by a bus are common to each device. And a separate unit having a structure for executing an individual function corresponding to each device. The common unit includes a host device interface serving as an interface corresponding to the host device. A debug interface for interfacing with a device for debugging, the debug interface of the common part of each of the plurality of devices is connected to a processing device such as a personal computer for debugging, and each processing device connected to the device A LAN for connecting to a processing device such as a personal computer provided in another different place is provided, and A debugging method for a device constituting a multiprocessor system, wherein a designated one of the plurality of devices is selected from a processing device such as a personal computer and the firmware of the individual unit is debugged. 2. The firmware according to claim 1, which executes the individual functions of the individual units of the plurality of devices, executes the program obtained by the execution result of the test via the debug interface, and processes the program on the personal computer or the like. A debugging method for a device constituting a multiprocessor system, characterized in that the device is downloaded to the individual unit via the debug interface.