CN117687856A

CN117687856A - Kernel detection method and device, electronic equipment and storage medium

Info

Publication number: CN117687856A
Application number: CN202311695162.7A
Authority: CN
Inventors: 杨雪敏
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2023-12-08
Filing date: 2023-12-08
Publication date: 2024-03-12

Abstract

The application discloses a kernel detection method, a kernel detection device, electronic equipment and a storage medium, relates to the technical field of computers, and is applied to a universal interrupt controller, wherein the universal interrupt controller comprises a plurality of redistributors, and the method comprises the following steps: enabling a redistributor corresponding to the kernel when receiving an enabling command of the kernel; acquiring a value of a processor sleep field in a power management control register in the redistributor; the method comprises the steps that a kernel sets a value of a processor sleep field to a first preset value before power-off, and sets the value of the processor sleep field to a second preset value after power-on; whether the core is in a power-on state is detected by the value of the processor sleep field. The method and the device realize that the universal interrupt controller detects whether the kernel is in the power-on state or not.

Description

Kernel detection method and device, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a method and apparatus for kernel detection, an electronic device, and a storage medium.

Background

In implementations of the GIC (Generic Interrupt Controller, general interrupt controller) architecture, the CPU (Central Processing Unit ) interface and the kernel are located in the same location power domain, but the CPU interface is different from the power domain in which the associated Redistributor is located. This means that Redistributor, distributor (the dispatcher) and its subsystems are powered up in the event that a core and its CPU interface may be powered down. In this case, the GIC architecture requires a power management function, sending a power-on event signaling mechanism to the kernel and CPU interface.

Therefore, how to implement the general interrupt controller to detect whether the kernel is in the power-on state is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The purpose of the application is to provide a kernel detection method and device, electronic equipment and storage medium, and to realize detection of whether a kernel is in a power-on state or not by a universal interrupt controller.

In order to achieve the above object, the present application provides a kernel detection method applied to a general interrupt controller, where the general interrupt controller includes a plurality of redistributors, the method includes:

enabling a redistributor corresponding to a kernel when an enabling command of the kernel is received;

acquiring a value of a processor sleep field in a power management control register in the redistributor; the method comprises the steps that the kernel sets the value of a processor sleep field to a first preset value before power-off, and sets the value of the processor sleep field to a second preset value after power-on;

and detecting whether the kernel is in a power-on state or not through the value of the processor sleep field.

Wherein, still include:

when the redistributor receives a power-off notification sent by the kernel, the redistributor sets the value of the processor sleep field to the first preset value;

And after the kernel sets itself to a power-down state, setting a kernel state field in the power management control register to the first preset value.

Wherein, still include:

when the redistributor needs to wake up the kernel, the redistributor sets the value of the processor sleep field to the second preset value so as to wake up the kernel; after the kernel wakes up successfully, setting a kernel state field in the power management control register to be the second preset value;

judging whether the kernel state field is the second preset value or not; if yes, the kernel is powered on successfully.

Wherein the detecting, by the value of the processor sleep field, whether the core is in a powered-on state includes:

detecting whether all the cores corresponding to all the redistributors are in a power-on state or not through the values of the sleep fields of the processors in the power management control registers in all the redistributors in the universal interrupt controller at preset intervals;

and outputting a kernel identification number corresponding to the kernel in the power-down state.

The core calculates the address of the corresponding redistributor according to the core identification number, and sends an enabling command to the redistributor according to the address of the redistributor so as to enable the redistributor.

The kernel calculates the address of the corresponding redistributor according to the kernel identification number, which comprises the following steps:

the kernel calculates the address of the redistributor corresponding to the kernel based on a redistributor address calculation formula; the redistribution address calculation formula specifically comprises:

addr2＝addr1+AR×(4+(2×ITScount)+(2×RDnum)；

wherein addr2 is the address of the redistributor obtained by calculation, addr1 is the base address of the universal interrupt controller, AR is the address range of the register set, ITScount is the total number of interrupt translation services, and Rdnum is the kernel identification number.

Wherein the enabling the redistribution corresponding to the kernel includes:

determining a redistributor corresponding to the kernel;

determining a power register in a redistributor corresponding to the kernel;

enabling the redistributors corresponding to the cores through a first control mode or a second control mode;

wherein executing enabling operation on the redistributors corresponding to the kernels in the first control manner includes:

determining a power-on and power-off control field in the power register, and setting the power-on and power-off control field to the second preset value;

determining an application cluster field in the power register, and setting the application cluster field to the second preset value;

If the power-on and power-off control field and the application cluster field are both the second preset value, enabling a redistributor corresponding to the kernel;

wherein executing enabling operation on the redistributors corresponding to the kernels in the second control manner includes:

determining an application cluster field in the power register, and setting the application cluster field to be the first preset value;

and if the power-on and power-off control field is the second preset value and the application cluster field is the first preset value, enabling all redistributors in the universal interrupt controller.

In order to achieve the above object, the present application provides a core detection apparatus applied to a general interrupt controller including a plurality of redistributors, the apparatus including:

the enabling module is used for enabling the redistributors corresponding to the kernels when an enabling command of the kernels is received;

an acquisition module for acquiring a value of a processor sleep field in a power management control register in the redistributor; the method comprises the steps that the kernel sets the value of a processor sleep field to a first preset value before power-off, and sets the value of the processor sleep field to a second preset value after power-on;

And the detection module is used for detecting whether the kernel is in a power-on state or not through the value of the sleep field of the processor.

The kernel calculates the address of the corresponding redistributor based on a redistributor address calculation formula; the redistribution address calculation formula specifically comprises:

addr2＝addr1+AR×(4+(2×ITScount)+(2×RDnum)；

Wherein, the enabling unit is specifically used for: and setting the power-on and power-off control field and the application cluster field in the power register in the redistributor corresponding to the kernel as the second preset value so as to enable the redistributor corresponding to the kernel.

Wherein, the enabling unit is specifically used for: setting the power-on and power-off control field in the power register in the redistributor corresponding to the kernel as the second preset value, and setting the application cluster field in the power register as the first preset value so as to enable all redistributors in the universal interrupt controller.

Wherein, still include:

the power-off module is used for setting the value of the processor dormancy field to the first preset value when the redistributor receives the power-off notification sent by the kernel; and after the kernel sets itself to a power-down state, setting a kernel state field in the power management control register to the first preset value.

Wherein, still include:

the power-on module is used for setting the value of the processor dormancy field to the second preset value when the redistributor needs to wake up the kernel so as to wake up the kernel; after the kernel wakes up successfully, setting a kernel state field in the power management control register to be the second preset value; judging whether the kernel state field is the second preset value or not; if yes, the kernel is powered on successfully.

Wherein, the detection module is specifically used for: detecting whether all the cores corresponding to all the redistributors are in a power-on state or not through the values of the sleep fields of the processors in the power management control registers in all the redistributors in the universal interrupt controller at preset intervals; and outputting a kernel identification number corresponding to the kernel in the power-down state.

To achieve the above object, the present application provides an electronic device, including:

a memory for storing a computer program;

and the processor is used for realizing the steps of the kernel detection method when executing the computer program.

To achieve the above object, the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the kernel detection method as described above.

According to the scheme, the kernel detection method is applied to a universal interrupt controller, the universal interrupt controller comprises a plurality of redistributors, and the method comprises the following steps: enabling a redistributor corresponding to a kernel when an enabling command of the kernel is received; acquiring a value of a processor sleep field in a power management control register in the redistributor; the method comprises the steps that the kernel sets the value of a processor sleep field to a first preset value before power-off, and sets the value of the processor sleep field to a second preset value after power-on; and detecting whether the kernel is in a power-on state or not through the value of the processor sleep field.

In the present application, the power management control register of the redistributor includes a processor sleep field, where the core sets the value of the processor sleep field to a first preset value before power is off, and sets the value of the processor sleep field to a second preset value after power is on, so that the redistributor can detect whether the corresponding core is in a power-on state by querying the value of the processor sleep field. The application also discloses a kernel detection device, electronic equipment and a computer readable storage medium, and the technical effects can be achieved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:

FIG. 1 is a diagram of a GIC assembly architecture, shown in accordance with an exemplary embodiment;

FIG. 2 is a flowchart illustrating a method of kernel detection, according to an example embodiment;

FIG. 3 is a flowchart illustrating a power down operation of a CPU interface and a kernel in a universal interrupt controller according to an exemplary embodiment;

FIG. 4 is a flowchart illustrating a power-on operation of a CPU interface and a kernel in a universal interrupt controller according to an exemplary embodiment;

FIG. 5 is a block diagram of a core detection apparatus according to an example embodiment;

fig. 6 is a block diagram of an electronic device, according to an example embodiment.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. In addition, in the embodiments of the present application, "first," "second," and the like are used to distinguish similar objects, and are not necessarily used to describe a particular order or sequence.

Because of the number of peripheral devices and interrupts associated with the peripheral devices in an SOC (System on Chip), and the number of different configurations for each interrupt, in order to reduce the burden on the CPU, the configuration and management of interrupts for a modern processor are generally implemented by an interrupt controller. To implement the interrupt configuration, receiving, arbitration, and routing functions, gic v3 designed different components, including four interrupt types, SPI (shared peripheral interrupt, public peripheral interrupt), PPI (private peripheral interrupt ), SGI (software generated interrupt, inter-core soft interrupt), and LPI (Locality-specific Peripheral Interrupt, peripheral interrupt in a specific location), and distributor, redistributor, ITS (Interrupt Translation Service ) and CPU interface. The SPI interrupt type is not tied to a particular CPU and can be routed to any CPU or group of particular CPUs depending on the register configuration. The PPI interrupt type is per processor private, i.e. a particular interrupt will only be routed to a particular processor, and its same interrupt number may have different interrupts on each processor, which may be triggered independently and handled independently by the particular processor. The SGI interrupt type does not have an actual physical connection, but is triggered by software by writing a register, which only supports edge triggering, typically for communication between processors. The LPI interrupt type is a message-based interrupt that a peripheral device does not need to connect to the GIC through a hardware interrupt line, but can write a message to a specific address to trigger the interrupt. After the interrupt is triggered by the peripheral device or software, the Distributor register and the Redistributor register distribute the interrupt to a specific CPU interface according to configuration information such as grouping, priority and the like of the interrupt, and send the interrupt to a corresponding kernel in an Interrupt (IRQ) or fast interrupt (FIQ, fast Interrupt Request) mode, at this time, the interrupt is in a suspended state, software on the kernel can answer the interrupt by reading the interrupt register, and the interrupt becomes an active state after being answered. After the interrupt processing is completed, the software makes the interrupt inactive by writing a specific register. If it is desired to know whether an interrupt is in a pending state, either the GICD_ISPENDR or GICD_ICPENDR register may be read; if it is desired to know whether the interrupt is in an active state, either the GICD_ ISACTIVER or GICD_ ICACTIVER registers may be read, with the two registers having bits to suspend the interrupt and clear the interrupt to control the interrupt's active state.

The currently commercially available GIC interrupt controller V2 version, the GIC cd (Generic Interrupt Controller Distributor, universal interrupt controller distributor), the GIC r (Generic Interrupt Controller Redistributor, universal interrupt controller redistributor), the CPU interface are all integrated in the GIC interrupt controller. The GIC v3 version separates the CPU interfaces from the GIC, allocates to each core, how many cores there are, and correspondingly how many CPU interfaces there are. The GIC can be divided into several different components, and each component will support one or more programming interfaces, which in turn can be divided into two classes, a memory mapped register interface and a system register interface. Wherein Distributor, redistributor is a memory mapped register interface and the CPU interface is a system register interface. The Distributor mainly comprises two parts of functions: (1) Some global properties of the interrupt controller and properties of the SPI-type interrupt may be configured through the GICD register as a programming interface. (2) When the interrupt is triggered, SPI and SGI interrupts are routed to a specific Redistributor and CPU interface according to the interrupt grouping, priority, affinity and other configurations set by the register. The Redistributor is located between the Redistributor and the CPU interface, and also comprises the following two functions: (1) The programming interface can be used for configuring the attribute of PPI and SGI type interrupts through a GICR register so as to set the configuration of interrupt trigger type, interrupt enable, interrupt priority and the like. At the same time, it also includes power management, LPI interrupt management functions (2) to send the highest priority pending interrupt to its corresponding CPU interface. Unlike the interrupt attribute of the SPI in the distributor, the interrupt attribute settings of the PPI and SGI are located in the redistributor, such as interrupt enable, priority, trigger mode, packet-to-interrupt state transition, etc., and the settings of the PPI and SGI interrupts are similar to the settings of the SPI except for the different registers. The CPU interface may be used for physical interrupt, virtual interrupt handling. Including SGI interrupt generation, PPI, priority setting of SGI, highest priority read, acknowledgement, interrupt clearing, completion of operation execution, etc.

As shown in FIG. 1, the system is powered on, and the CPU interface needs to be connected with the Redistributor in the GIC, so that after the system is powered on, the CPU interface in the kernel is connected with the Redistributor in the GIC, and the GIC can send an interrupt to the kernel in the future.

The CPU interface and the GIC belong to different power domains, so that a user can conveniently close the unused cores according to different use scenes to achieve the purpose of saving power consumption or other requirements. The on-off of the CPU interface power supply is controlled by the GICR register, and the GICR base addresses corresponding to each kernel are different, so that a safe and convenient mode is needed to access the GIC to achieve the purpose of detecting the kernel power supply.

The main purpose of this application is to detect the condition of powering up of every nuclear to under the condition of not powering up, send out information according to certain frequency, indicate the user, prevent that this nuclear from not powering up and the interrupt that leads to can't respond the problem when using appear for the user. The power-on information of the target core is obtained through real-time detection, so that a user can know the power-on condition of the core, and good man-machine interaction is realized.

The embodiment of the application discloses a kernel detection method, which realizes that a general interrupt controller detects whether a kernel is in a power-on state or not.

Referring to fig. 2, a flowchart of a kernel detection method according to an exemplary embodiment is shown, as shown in fig. 2, including:

s101: enabling a redistributor corresponding to a kernel when an enabling command of the kernel is received;

in a specific implementation, after the power is reset, the Redistributor defaults to a power-down state, and then the Redistributor must be enabled first, and then the Redistributor is connected with the CPU interface through a specific register in the Redistributor register group, and then the GIC interrupts normal operation.

As a possible implementation manner, the kernel calculates the address of the corresponding redistributor according to the kernel identification number, and sends an enabling command to the redistributor according to the address of the redistributor so as to enable the redistributor.

In a specific implementation, the Redistributor of each core is powered up separately. Because the addresses of the redistributors connected with each core are inconsistent on the bus, in actual operation, the address of the redistributor is calculated by acquiring the ID of the core, and the calculation formula of the redistributor address is specifically as follows:

addr2＝addr1+AR×(4+(2×ITScount)+(2×RDnum)；

Further, the kernel enables the redistributors according to the addresses of the corresponding redistributors. As a possible implementation manner, the enabling the redistribution device corresponding to the kernel includes: determining a redistributor corresponding to the kernel; determining a power register in a redistributor corresponding to the kernel; determining a power-on and power-off control field in the power register, and setting the power-on and power-off control field to the second preset value; determining an application cluster field in the power register, and setting the application cluster field to the second preset value; and if the power-on and power-off control field and the application cluster field are both the second preset value, enabling a redistributor corresponding to the kernel.

In an implementation, each core programs the corresponding gicr_pwrr register to make the power-up and power-down control field (gicr_pwrr.rdpd) and the application cluster field (gicr_pwrr.rdag) in the power register in the Redistributor to be a second preset value, for example, to make gicr_pwrr.rdpd=0 and gicr_pwrr.rdag=0, to ensure that the Redistributor is powered up, and gicr_pwrr.rdpd and gicr_pwrr.rdag are control fields in the register, and have corresponding addresses on the bus.

As another possible implementation manner, the enabling the redistribution device corresponding to the kernel includes: determining a redistributor corresponding to the kernel; determining a power register in a redistributor corresponding to the kernel; determining a power-on and power-off control field in the power register, and setting the power-on and power-off control field to the second preset value; determining an application cluster field in the power register, and setting the application cluster field to be the first preset value; and if the power-on and power-off control field is the second preset value and the application cluster field is the first preset value, enabling all redistributors in the universal interrupt controller.

In an implementation, each core enables the redistributors of all cores by writing the gicr_pwrr register such that gicr_pwrr.rdpd=0 and gicr_pwrr.rdag=1, and the power management register of the GICR may control the Redistributor power management by core operation or by the register operation of the redistributors.

S102: acquiring a value of a processor sleep field in a power management control register in the redistributor; the method comprises the steps that the kernel sets the value of a processor sleep field to a first preset value before power-off, and sets the value of the processor sleep field to a second preset value after power-on;

In particular implementations, the core interrupts a power management control register (Generic Interrupt Controller Redistributor Power Management Control Register, gicr_wake) in the controller redistributor prior to powering down, sets a processor sleep field (processor sleep) value to a first preset value, sets the processor sleep field value to a second preset value after powering up, e.g., sets the processor sleep field value to 1 prior to powering down, and sets the processor sleep field value to 0 after powering up. Thus, the value of the processor sleep field in the power management control register in the redistributor may be obtained when it is desired to detect whether the core is in a powered-up state.

S103: and detecting whether the kernel is in a power-on state or not through the value of the processor sleep field.

In a specific implementation, whether the kernel is in a power-on state is detected through the value of the processor sleep field, the kernel is in the power-on state when the value of the processor sleep field is a second preset value, and the kernel is in a power-off state when the value of the processor sleep field is a first preset value. For example, the core is in a power-up state when the value of the processor sleep field is 0, and the core is in a power-down state when the value of the processor sleep field is 1.

As a preferred embodiment, the detecting whether the core is in a power-on state by the value of the processor sleep field includes: detecting whether all the cores corresponding to all the redistributors are in a power-on state or not through the values of the sleep fields of the processors in the power management control registers in all the redistributors in the universal interrupt controller at preset intervals; and outputting a kernel identification number corresponding to the kernel in the power-down state.

It will be appreciated that for a multi-core configuration system, all cores are in a powered-up, ready-to-use state after the GIC is started. According to the use scene, not all the cores participate in the work, and the use effect is not affected and the energy consumption can be saved by turning off part of the cores. The kernel after power failure no longer participates in the interrupt response, but its corresponding redistributor register still works normally. And inquiring the value of the sleep field of the processor in the power management control register in each redistributor every preset period to detect whether the corresponding core is in a power-on state, and outputting a core identification number of the core in a power-off state to a user for real-time feedback, so that resources are saved and a good man-machine interaction effect is achieved.

In this embodiment of the present application, the power management control register of the redistributor includes a processor sleep field, where before the kernel is powered off, the value of the processor sleep field is set to a first preset value, and after the kernel is powered on, the value of the processor sleep field is set to a second preset value, so that the redistributor can detect whether the corresponding kernel is in a powered-on state by querying the value of the processor sleep field.

The present embodiment describes a power-off operation of a CPU interface and a kernel in a general interrupt controller, and specifically:

referring to FIG. 3, a flowchart of a power down operation of a CPU interface and a kernel in a universal interrupt controller is shown according to an exemplary embodiment, as shown in FIG. 3, comprising:

s201: when the redistributor receives a power-off notification sent by the kernel, the redistributor sets the value of the sleep field of the processor to a first preset value;

s202: after the kernel sets itself to the power down state, the kernel status field in the power management control register is set to a first preset value.

In particular implementations, the software notifies the Redistributor before the CPU interface and kernel are to be powered down: the CPU interface and the kernel are to enter a low-power state (power down state). A write 1 to the Processosleep field of the GICR_WAKER register indicates that the kernel is to enter the low-power state. After the CPU interface sets itself to the low-power state, the ChildrenAnasep field is set to 1. When the child sleep field is 1, the Redistributor will not send an interrupt to the CPU interface, nor will the Redistributor consider the core in interrupt arbitration.

The present embodiment describes a power-on operation of a CPU interface and a kernel in a general interrupt controller, and specifically:

referring to FIG. 4, a flowchart of the power-on operation of the CPU interface and the kernel in a universal interrupt controller is shown according to an exemplary embodiment, as shown in FIG. 4, comprising:

s301: when the redistributor needs to wake up the kernel, the redistributor sets the value of the sleep field of the processor to a second preset value so as to wake up the kernel; after the kernel wakes up successfully, setting a kernel state field in a power management control register to be a second preset value;

s302: judging whether the kernel state field is a second preset value or not; if yes, the kernel is powered on successfully.

In an implementation, the GICR_WAKER register is also operated when the GIC is to wake up the CPU interface and the kernel. And writing the Processor sleep field into 0, then waking up the CPU, finally reading the ChildrenAnasep field, judging whether the kernel wakes up successfully, and if the ChildrenAnasep field is 0, indicating that the GIC interrupt can work normally on the kernel.

The following describes a core detection apparatus provided in the embodiments of the present application, and a core detection apparatus described below and a core detection method described above may be referred to each other.

Referring to fig. 5, a block diagram of a core detection apparatus according to an exemplary embodiment is shown, as shown in fig. 5, including:

an enabling module 501, configured to enable a redistributor corresponding to a kernel when an enabling command of the kernel is received;

An obtaining module 502, configured to obtain a value of a processor sleep field in a power management control register in the redistributor; the method comprises the steps that the kernel sets the value of a processor sleep field to a first preset value before power-off, and sets the value of the processor sleep field to a second preset value after power-on;

A detecting module 503, configured to detect, by using the value of the processor sleep field, whether the core is in a power-on state.

On the basis of the above embodiment, as a preferred implementation manner, the method further includes:

Based on the above embodiment, as a preferred implementation manner, the detection module 503 is specifically configured to: detecting whether all the cores corresponding to all the redistributors are in a power-on state or not through the values of the sleep fields of the processors in the power management control registers in all the redistributors in the universal interrupt controller at preset intervals; and outputting a kernel identification number corresponding to the kernel in the power-down state.

On the basis of the above embodiment, as a preferred implementation manner, the kernel calculates the address of the corresponding redistributor according to the kernel identification number, and sends an enabling command to the redistributor according to the address of the redistributor so as to enable the redistributor.

Based on the above embodiment, as a preferred implementation manner, the kernel calculates the address of the corresponding redistributor based on a redistributor address calculation formula; the redistribution address calculation formula specifically comprises:

addr2＝addr1+AR×(4+(2×ITScount)+(2×RDnum)；

On the basis of the above embodiment, as a preferred implementation manner, the enabling unit 501 is specifically configured to: determining a redistributor corresponding to the kernel; determining a power register in a redistributor corresponding to the kernel; enabling the redistributors corresponding to the cores through a first control mode or a second control mode; wherein executing enabling operation on the redistributors corresponding to the kernels in the first control manner includes: determining a power-on and power-off control field in the power register, and setting the power-on and power-off control field to the second preset value; determining an application cluster field in the power register, and setting the application cluster field to the second preset value; if the power-on and power-off control field and the application cluster field are both the second preset value, enabling a redistributor corresponding to the kernel; wherein executing enabling operation on the redistributors corresponding to the kernels in the second control manner includes: determining a power-on and power-off control field in the power register, and setting the power-on and power-off control field to the second preset value; determining an application cluster field in the power register, and setting the application cluster field to be the first preset value; and if the power-on and power-off control field is the second preset value and the application cluster field is the first preset value, enabling all redistributors in the universal interrupt controller.

In a specific implementation, the first control manner is: each core programs the corresponding gicr_pwrr register to make the power-up and power-down control field (gicr_pwrr.rdpd) and the application cluster field (gicr_pwrr.rdag) in the power register in the Redistributor to be a second preset value, for example, to make gicr_pwrr.rdpd=0 and gicr_pwrr.rdag=0, so as to ensure that the Redistributor is powered up, and gicr_pwrr.rdpd and gicr_pwrr.rdag are control fields in the register, and have corresponding addresses on the bus.

The second control mode is as follows: each core enables the redistributors of all cores by writing the gicr_pwrr register such that gicr_pwrr.rdpd=0 and gicr_pwrr.rdag=1, and the power management register of the GICR can control the Redistributor power management by the core operation or by the register operation of the redistributors.

The specific manner in which the various modules perform the operations in the apparatus of the above embodiments have been described in detail in connection with the embodiments of the method, and will not be described in detail herein.

Based on the hardware implementation of the program modules, and in order to implement the method of the embodiments of the present application, the embodiments of the present application further provide an electronic device, fig. 6 is a block diagram of an electronic device according to an exemplary embodiment, and as shown in fig. 6, the electronic device includes:

A communication interface 1 capable of information interaction with other devices such as network devices and the like;

and the processor 2 is connected with the communication interface 1 to realize information interaction with other devices and is used for executing the kernel detection method provided by one or more technical schemes when running the computer program. And the computer program is stored on the memory 3.

Of course, in practice, the various components in the electronic device are coupled together by a bus system 4. It will be appreciated that the bus system 4 is used to enable connected communications between these components. The bus system 4 comprises, in addition to a data bus, a power bus, a control bus and a status signal bus. But for clarity of illustration the various buses are labeled as bus system 4 in fig. 6.

The memory 3 in the embodiment of the present application is used to store various types of data to support the operation of the electronic device. Examples of such data include: any computer program for operating on an electronic device.

It will be appreciated that the memory 3 may be either volatile memory or nonvolatile memory, and may include both volatile and nonvolatile memory. Wherein the nonvolatile Memory may be Read Only Memory (ROM), programmable Read Only Memory (PROM, programmable Read-Only Memory), erasable programmable Read Only Memory (EPROM, erasable Programmable Read-Only Memory), electrically erasable programmable Read Only Memory (EEPROM, electrically Erasable Programmable Read-Only Memory), magnetic random access Memory (FRAM, ferromagnetic random access Memory), flash Memory (Flash Memory), magnetic surface Memory, optical disk, or compact disk Read Only Memory (CD-ROM, compact Disc Read-Only Memory); the magnetic surface memory may be a disk memory or a tape memory. The volatile memory may be random access memory (RAM, random Access Memory), which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (SRAM, static Random Access Memory), synchronous static random access memory (SSRAM, synchronous Static Random Access Memory), dynamic random access memory (DRAM, dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory (ddr SDRAM, double Data Rate Synchronous Dynamic Random Access Memory), enhanced synchronous dynamic random access memory (ESDRAM, enhanced Synchronous Dynamic Random Access Memory), synchronous link dynamic random access memory (SLDRAM, syncLink Dynamic Random Access Memory), direct memory bus random access memory (DRRAM, direct Rambus Random Access Memory). The memory 3 described in the embodiments of the present application is intended to comprise, without being limited to, these and any other suitable types of memory.

The method disclosed in the embodiments of the present application may be applied to the processor 2 or implemented by the processor 2. The processor 2 may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in the processor 2 or by instructions in the form of software. The processor 2 described above may be a general purpose processor, DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. The processor 2 may implement or perform the methods, steps and logic blocks disclosed in the embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in the embodiments of the present application may be directly embodied in a hardware decoding processor or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium in the memory 3 and the processor 2 reads the program in the memory 3 to perform the steps of the method described above in connection with its hardware.

The processor 2 implements corresponding flows in the methods of the embodiments of the present application when executing the program, and for brevity, will not be described in detail herein.

In an exemplary embodiment, the present application also provides a storage medium, i.e. a computer storage medium, in particular a computer readable storage medium, for example comprising a memory 3 storing a computer program executable by the processor 2 for performing the steps of the method described above. The computer readable storage medium may be FRAM, ROM, PROM, EPROM, EEPROM, flash Memory, magnetic surface Memory, optical disk, CD-ROM, etc.

Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware associated with program instructions, where the foregoing program may be stored in a computer readable storage medium, and when executed, the program performs steps including the above method embodiments; and the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.

Alternatively, the integrated units described above may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in essence or a part contributing to the prior art in the form of a software product stored in a storage medium, including several instructions for causing an electronic device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of core detection for use with a universal interrupt controller, the universal interrupt controller comprising a plurality of redistributors, the method comprising:

2. The kernel detection method as recited in claim 1, further comprising:

3. The kernel detection method as recited in claim 1, further comprising:

4. The core detection method of claim 1, wherein the detecting whether the core is in a powered-up state by the value of the processor sleep field comprises:

5. The core detection method according to claim 1, wherein the core calculates an address of a corresponding redistributor based on a core identification number, and transmits an enable command to the redistributor based on the address of the redistributor so as to enable the redistributor.

6. The core detection method according to claim 5, wherein the core calculates an address of a corresponding redistributor according to a core identification number, comprising:

addr2＝addr1+AR×(4+(2×ITScount)+(2×RDnum)；

7. The kernel detection method as recited in claim 1, wherein the enabling the re-dispatcher corresponding to the kernel comprises:

determining a redistributor corresponding to the kernel;

determining a power register in a redistributor corresponding to the kernel;

8. A core detection apparatus for use with a universal interrupt controller, the universal interrupt controller comprising a plurality of redistributors, the apparatus comprising:

9. An electronic device, comprising:

a memory for storing a computer program;

processor for implementing the steps of the kernel detection method as claimed in any one of claims 1 to 7 when executing the computer program.

10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the kernel detection method as claimed in any one of claims 1 to 7.