JPH04219847A - Device and method for monitoring and disconnecting bus abnormality - Google Patents

Abstract

PURPOSE:To detect the continuation of bus occupation by a specific unit and disconnect a faulty unit by a processor where many units having bus control right are connected to one bus. CONSTITUTION:Each unit which outputs a bus request to a bus control unit 3 from a bus switching circuit 4 and occupies the common bus 2 corresponding to a bus occupation permission signal sent back from a bus priority decision circuit 6 is provided with a bus busy state monitor circuit 5 and the bus request signal is cut off after a constant time from the output of the bus busy state signal is clocked to stop the bus busy state signal. Further, the bus control unit is provided with a bus control decision circuit 7 to latch the bus occupation permission signal, provided with a bus monitor circuit 8 to clock the constant time after the generation of the bus busy state signal, and also provided with a bus request gate circuit 9 to cut off the input of the bus request signal corresponding to the latched bus occupation permission signal after the constant time is counted.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a device and method for monitoring abnormalities in buses and disconnecting them, and in particular, the present invention relates to bus abnormality monitoring and abnormality triggering when a unit fails while occupying the bus in a monitoring/control computer system. The present invention relates to a bus abnormality monitoring/disconnection device and method for disconnecting the bus.

[0002] In recent years, control computer systems are required to have more sophisticated processing and non-stop processing. As processing becomes more sophisticated, systems are constructed using multiple CPUs (central processing units).
In order to reduce the load on the CPU, an increasing number of systems are using a large number of IO units that operate intelligently. These units are generally connected by a single bus, but depending on the failure mode of the unit, the bus may remain occupied, resulting in the failure of one unit causing the entire system to go down. It may happen.

[0003] Therefore, in a processing device in which a large number of units are connected to one bus, it is desired to prevent the influence of failure of some units from spreading to the entire system.

0004

[Prior Art] In a conventional system, a unit (bus master) that has bus control over one bus
were never connected in large numbers. Therefore, the unit's tripping function, which corresponds to the aforementioned failure mode, was not considered. In addition, since the scale of the system is small,
Even if it broke down, it wasn't a big problem.

[0005]

[Problem to be Solved by the Invention] However, in recent years, as the number of bus masters has increased in systems, devices with multiple functions have come to be configured even in one system, and it is required to avoid the above-mentioned failures. It became so.

[0006] The present invention aims to solve the problems of the prior art as described above.
The object of the present invention is to provide a bus abnormality monitoring/disconnection method that detects that a specific unit remains occupying the bus and can remove a faulty unit.

[0007]

[Means for Solving the Problems] The present invention provides a system in which when a plurality of units having bus control rights are connected to one common bus and a bus request is generated in each unit, a bus switching circuit sends a request to a bus management unit. It outputs a bus request signal, and in the bus management unit, the bus priority determination circuit determines the signal priority of each bus request signal and occupies the bus according to the generated bus occupancy permission signal, and also generates a bus busy signal to In a processing device that notifies other units of the occupancy state, each unit having bus control counts a certain period of time from the output of the bus busy signal, and at the end of the counting, outputs the bus request signal from the bus switching circuit. This is characterized by the provision of a bus busy monitoring circuit that interrupts the bus busy signal and stops the bus busy signal. In this case, the bus management unit includes a bus control determination circuit that latches the bus occupancy permission signal, a bus busy monitoring circuit that counts a certain period of time from the generation of the bus busy signal, and when the bus busy monitoring circuit finishes counting, the bus control determination circuit latches the bus occupancy permission signal. The present invention is characterized in that it includes a bus request gate circuit that blocks input of a bus request signal corresponding to a bus occupancy permission signal latched in the circuit.

[0008]

[Operation] Fig. 1 shows the basic configuration of the present invention, in which 11, 12,..., 1n+1 are units having bus control, 2 is a common bus, and 3 is a bus that manages the common bus. It is a management unit. In the units 11, 12, . In the bus management unit 3, 6 determines the priority according to the bus request signal *BREQ from the unit having bus mastery and outputs a bus occupation permission signal *BPRN to the unit having bus mastery. This is a bus priority determination circuit. Reference numeral 7 denotes a bus dominance determination circuit that determines whether the bus dominance state continues. 8 is a bus busy monitoring circuit that monitors bus busy time. Reference numeral 9 denotes a bus request gate circuit that gates the input of the bus request signal *BREQ to the bus priority determination circuit 6.

Units 11, 12, which have bus control rights,
..., 1n+1 is determined by the bus request signal *BREQ,
A bus occupancy request is notified to the bus management unit 3, and bus control is granted by the bus occupancy permission signal *BPRN from the bus management unit 3. While the bus is in use, the bus occupancy state is set by outputting the bus busy signal *BUSY. hold.

Units 11, 12, which have bus control rights,
. Performs the process of releasing the unit from the control of its own unit to another party. At this time, the bus busy monitoring circuit 5 monitors the bus busy time, and if the busy state continues for a certain period of time or more,
The unit determines that it is a failure, generates a reset signal, and resets the unit to release the bus from occupancy.

In the bus management unit 3, the bus control determination circuit 7 determines whether a unit having specific bus control is
It is determined that the bus request signal *BREQ continues to be output. At this time, if the bus busy monitoring circuit 8 detects that the bus busy signal *BUSY continues for a certain period of time or more, the bus request gate circuit 9 is controlled to block input of the bus request signal *BREQ. As a result, the bus occupancy permission signal *BPRN for the unit having the specific bus mastership that continues to request the bus is turned off, and the bus occupancy by this specific unit is released. In this case,
The unit with bus control sends the bus request signal *BREQ.
continues to be output for more than a certain period of time only when the unit with bus mastery is in failure, and normally the bus request signal *BREQ is output so that it does not continue to be output even if multiple bus requests occur. are taken into account in the system.

0012

[Embodiment] FIG. 2 is a diagram showing the configuration of a unit having bus mastership according to an embodiment of the present invention, in which parts having the same functions as in FIG. , 41, 42, 43 are flip-flops (
FF), 44 and 45 are gates. Further, 21 is a bus busy line, and 22 is a bus clock line.

Units 11, 12, which have bus control
...1n+1 performs DMA transfer of data to the common bus 2 in a bus occupied state. The bus management unit 3 receives bus request signals *BREQ0, *BREQ from each unit.
1, ..., *BREQn, the priority order is determined by the parallel priority determination method, and the bus occupancy permission signal *BP is sent to the determined unit, for example, unit 11.
Output RN0. While the bus is in use, the unit 11 outputs a bus busy signal *BUSY to the bus busy line 21.

When an intra-unit bus request occurs in the unit 11, the bus exchange circuit 4 outputs the bus request signal *BREQ via the FFs 41 and 42 in response to the clock signal *BCLK applied from the bus clock line 22.
0 is generated and sent to the bus management unit 3. Initially, the bus busy monitoring circuit 5 is in a reset state. At this time, since the FF 43 is outputting "L" to the Q terminal, the bus busy signal *BUSY is in the "H" state indicating that it is not used.

Bus request signal *BR from unit 11
For the EQ, when the priority determination result in the bus management unit 3, the bus occupancy permission signal *BPRN0, is returned, the bus busy signal *BU from all other units
The unit 11 acquires the right to use the common bus 2 on the condition that SY is in the "H" state indicating non-use. At this time, an output is generated from the gate 44 and the FF 43
The Q output of is held at “H” and the bus busy signal *BUS
Y becomes "L" indicating use.

When the intra-unit bus request disappears, the set signal S applied from the gate 45 becomes "L", so the FF 43 is released from holding and the bus busy signal *BU is released.
SY becomes "H" state indicating non-use.

In the bus busy monitoring circuit 5, the timer 5
1 starts counting when the Q output of the FF 43 becomes "H", and when a predetermined time elapses, generates a time-out signal and resets the FF 43. This prevents the unit 11 from continuing to occupy the common bus 2 due to a failure or the like. When the bus occupancy state is resolved within the predetermined time of the timer 51 and the hold on the FF 43 is released,
The timer 51 returns to the reset state and takes no action on the bus switching circuit 4.

FIG. 3 is a diagram showing the configuration of a bus management unit according to an embodiment of the present invention, in which parts having the same functions as in FIG. 1 are designated by the same numbers. Priority encoder, 62
is a decoder. In the bus dominance determination circuit 7, 71
is a latch circuit. In the bus busy monitoring circuit 8, 81 is a clock generator, and 82 is a counter. Further, in the bus request gate circuit 9, 910, 91
1, ..., 91n are flip-flops (FF), 920
, 921, ..., 92n are gates.

In the bus request gate circuit 9, each FF is in a reset state and outputs "H" in the initial state, so when a bus request signal is generated, an output is generated through the corresponding gate, and bus priority is given. The signal is input to the determination circuit 6. In the bus priority determination circuit 6, a priority encoder 61 generates an output according to the priority of the bus request, and a decoder 62 decodes this output to generate a bus occupancy permission signal corresponding to the bus request signal.

In the bus dominance determination circuit 7, the latch circuit 71 converts the bus occupancy permission signal into a bus busy signal *BUSY.
It is held on every bus exchange by latching on the falling edge of . In the bus busy monitoring circuit 8, the counter 82 is reset at the falling edge of the bus busy signal *BUSY, and by counting the clock of the clock generator 81, generates a timeout signal when the bus occupancy permission state continues for a certain period of time or more.

In the bus request gate circuit 9, the FF corresponding to the bus request generates an "L" output when the counter 82 counts up in response to the bus occupancy permission signal latched by the latch circuit 71. output is turned off. Therefore, the corresponding bus occupancy permission signal from the bus priority determination circuit 6 is also turned off, so that the unit that has continued to occupy the bus due to the occurrence of the fault is released from bus occupancy.

[0022] In the unit having bus control shown in FIG. 2, when the bus is occupied for a certain period of time or more, the specific unit is removed from the bus, and in the bus management unit shown in FIG. Since the removal of a specific unit from the bus when the bus is occupied is performed independently, it is also possible to use both protections in combination.

[0023]

As explained above, according to the present invention, in a processing device in which a large number of units having bus mastery (bus masters) are connected to one bus, it is possible to prevent a specific unit from monopolizing the bus. detects that
Since the failed unit can be removed, it is possible to prevent the system from going down due to an abnormality in the unit that has bus control.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is a diagram showing the configuration of a unit having bus control according to an embodiment of the present invention.

FIG. 3 is a diagram showing the configuration of a bus management unit according to an embodiment of the present invention.

[Explanation of symbols]

11, 12,..., 1n+1 Unit with bus dominance 2 Common bus 3 Bus management unit 4 Bus switching circuit 5 Bus busy monitoring circuit 6 Bus priority determination circuit 7 Bus dominance determination circuit 8 Bus busy monitoring circuit 9 Bus request gate circuit

Claims (3)

[Claims] [Claim 1] Units (11, 12,..., 1n+1) having a plurality of bus control rights over one common bus (2)
is connected and a bus request occurs in each unit, the bus switching circuit (4) outputs a bus request signal to the bus management unit (3), and the bus management unit (3)
The bus priority determination circuit (6) determines the signal priority of each bus request signal and occupies the bus according to the generated bus occupancy permission signal, and also generates a bus busy signal to notify the bus occupancy status to other units. The processing device that notifies each unit that has bus control rights counts a certain period of time from the output of the bus busy signal, and when the counting ends, cuts off the output of the bus request signal from the bus switching circuit (4), and issues a bus busy signal. A bus abnormality monitoring/disconnection device comprising a bus busy monitoring circuit (5) for stopping a signal. [Claim 2] Units (11, 12,..., 1n+1) having a plurality of bus control rights over one common bus (2)
is connected and a bus request occurs in each unit, the bus switching circuit (4) outputs a bus request signal to the bus management unit (3), and the bus management unit (3)
The bus priority determination circuit (6) determines the signal priority of each bus request signal and occupies the bus according to the generated bus occupancy permission signal, and also generates a bus busy signal to notify the bus occupancy status to other units. In the processing device that sends the notification, the bus management unit (3) includes a bus control determination circuit (7) that latches the bus occupancy permission signal, a bus busy monitoring circuit (8) that counts a certain period of time from the generation of the bus busy signal, and When the monitoring circuit (8) finishes counting,
A bus abnormality monitoring/disconnection device comprising: a bus request gate circuit (9) for blocking input of a bus request signal corresponding to a bus occupation permission signal latched to the bus control determination circuit (7). [Claim 3] Units (11, 12, . . . , 1n+1) having a plurality of bus control rights over one common bus (2).
is connected and a bus request occurs in each unit, the bus switching circuit (4) outputs a bus request signal to the bus management unit (3), and the bus management unit (3)
The bus priority determination circuit (6) determines the signal priority of each bus request signal and occupies the bus according to the generated bus occupancy permission signal, and also generates a bus busy signal to notify the bus occupancy status to other units. In the processing device that notifies, each unit having bus control counts a certain period of time from the output of the bus busy signal, and at the end of the counting, cuts off the output of the bus request signal from the bus switching circuit (4), and In the management unit (3), the bus occupancy permission signal is latched, and a certain period of time is counted from the generation of the bus busy signal, and when the counting is completed, the input of the bus request signal corresponding to the latched bus occupancy permission signal is cut off. A bus abnormality monitoring/disconnection method characterized by: