JPH04305758A - Information processor - Google Patents

Abstract

PURPOSE:To instantaneously execute the proper start of a slave processor and the detection of a fault. CONSTITUTION:A master processor 11 and slave processors 12, 13 are mutually connected through a master ready line 14b and a slave ready line 14c included in a common bus 14 and the master processor 11 applies a self-operation state (master operation state) to the line 14c. On the other hand, each of the slave processors 12, 13 applies a self-operation state (slave operation state) to the line 14c. The master processor 11 monitors the line 14c to know the operation states of the slave processors 12, 13 and each slave processor monitors the lines 14b, 14c to know the operation states of the master processor 11 and the other slave processor.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to startup and failure detection in an information processing apparatus having a multiprocessor configuration.

0002

2. Description of the Related Art Generally, this type of information processing apparatus includes a master processor and a slave processor. After power-up, the slave processor enters either a reset state, a halt state, or an interrupt state by performing self-diagnostics. On the other hand, after turning on the power, the master processor loads a program for operating the slave processor (simply referred to as a program) into the main storage device, and executes the first step or the second step. In the first step, the waiting time is set by the program count, thereby securing the self-diagnosis time for the slave processor, and the master processor determines that the self-diagnosis is completed after the waiting time has elapsed. , the master processor senses the status of each slave processor in turn and recognizes that it is in an interrupt wait state, then interrupts the slave processor and loads the program.

[0003] When the loading of the program is completed, the slave processor sets a completion flag in a common access area provided in the main memory, for example. On the other hand, when the master processor senses the common access area and confirms that the completion flag is set, it recognizes that the program load has been completed.

Furthermore, when a fault occurs in a slave processor, a fault flag is set in the common access area of the faulty slave processor. The master processor determines that a failure has occurred when the failure flag is set by sensing the common access area.

[0005]

[Problems to be Solved by the Invention] As mentioned above, when the master processor sets the wait time for self-diagnosis using the program count, the slave processor may not be able to wait for interrupts due to the performance of the master processor and slave processors. The master processor may execute an interrupt before the master processor enters the state, and as a result, there is a problem in that it is not possible to secure the optimal start-up time for the slave processor.

Furthermore, when the master processor senses the status of each slave processor and issues an interrupt, the master processor senses the slave processors in sequence, so as the number of slave processors increases, the number of interrupts increases depending on the number of slave processors. There is a problem that the raising time increases.

Furthermore, as mentioned above, since the master processor recognizes the completion of program loading to the slave processor and the detection of a fault by sensing the common access area, there is a problem that it takes time to complete the load and detect a fault. There is. In other words, there is a problem in that loading cannot be completed and failures cannot be detected immediately.

An object of the present invention is to provide an information processing apparatus that can appropriately start up a slave processor.

Another object of the present invention is to provide an information processing device that can immediately complete loading and detect failures.

0010

According to the present invention, in an information processing device in which a master processor and a slave processor are connected to each other, the master processor and the slave processor further have first and second processors connected to each other.
are interconnected by control lines, and the master processor includes a first sending means for sending a master operating state as a master operating state signal to the first control line, and a first sending means for monitoring the second control line. a first monitoring means, the slave processor is provided with a second sending means for sending a slave operating state as a slave operating state signal to the second control line; There is obtained an information processing apparatus characterized in that it is equipped with a second monitoring means for monitoring.

[0011]

EXAMPLES The present invention will be explained below by way of examples.

Referring to FIG. 1, the illustrated information processing apparatus includes a master processor 11 and a slave processor 12.
and 13. The master processor 11 connects to the slave processor 12 via the common bus 14.
and 13. The common bus 14 includes an address data control line 14a and a master ready line 14b.
, and a slave ready line 14c. The master processor 11 has an input/output (I/O) bus 1.
An I/O control device 16 is connected via 5. Furthermore, the memory 1 is connected to the address data control line 14a.
7 is connected. Note that although only the slave processors 12 and 13 are shown in FIG. 1, other slave processors may be connected to the common bus 14.

When the power is turned on, the microprocessor (MPU) 11a on the master processor 11 activates the master flip-flop (MF/
F) Reset 11b. This reset causes the master flip-flop 11b to send out a master inactive signal, and the driver 11c drives the master ready line 14b inactive.

Similarly, in slave processors 12 and 13, when power is turned on, microprocessors 12a and 13a reset slave flip-flops (SF/F) 12b and 13b, respectively. This reset causes the slave flip-flops 12b and 1
3b respectively send out first and second slave inactive signals, and the open collector driver 12c
and 13c drive the slave ready line 14c inactive.

In the slave processors 12 and 13, the microprocessors 12a and 13a recognize that the master ready line 14c is inactive by the receivers 12d and 13d, respectively.
After turning on the power and performing self-diagnosis, the microprocessors 12a and 13a wait for the master ready line 14c to become active. In other words, it is in a waiting state.

On the other hand, in the master processor 11, the program for operating the slave processor is transferred to the I/O control device 1.
6 and expands it onto the memory 17 via the address data control line 14a. Thereafter, the microprocessor 11a sets the master flip-flop 11b. As a result, master flip-flop 1
1b sends a master active signal and driver 1
1c activates the master ready line 14b.

At this stage, the slave processor 12
It is assumed that the slave processor 13 has completed its self-diagnosis and is in a waiting state, and the slave processor 13 is in the process of self-diagnosis. In the slave processor 12, when the microprocessor 12a recognizes via the receiver 12d that the master ready line 14b is active, the slave processor 12 accesses the common bus 14 and loads the program from the memory 17. On the other hand, the slave processor 13 is notified via the receiver 13d that the microprocessor 13a is informed that the master ready line 14b is active. Therefore, the slave processor 13 accesses the common bus 14 and loads the program from the memory 17 immediately after the self-diagnosis is completed.

When the loading of the program is completed, in the slave processor 12, the microprocessor 12a sets the slave flip-flop 12b. As a result, the slave flip-flop 12b sends out an active signal, and the open collector driver 12
c actively drives the slave ready line 14c. On the other hand, in this state, the slave processor 13
Since the program is being loaded, the open collector driver 13c is inactively driving the slave ready line 14c. Therefore, the slave ready line 14c remains inactive, and in the master processor 11, the receiver 11d causes the microprocessor 11a to read the slave ready line 14.
It is recognized that c is in an inactive state. Similarly, in slave processor 12, receiver 1
2e, the microprocessor 12a recognizes that the slave ready line 14c is inactive, and the slave processor 12 does not access other processors.

When the loading of the program is completed, in the slave processor 13, the microprocessor 13a sets the slave flip-flop 13b. As a result, the slave flip-flop 13b sends out an active signal, and the open collector driver 13
c actively drives the slave ready line 14c. As a result, the slave ready line 14c becomes active.

As a result, the master processor 11 recognizes by the receiver 11d that the slave ready line 14c has become active. Similarly, in slave processors 12 and 13, receivers 12e and 1
3e, the microprocessors 12a and 13a recognize that the slave ready line 14c has become active. In other words, all processors recognize that the loading of the program to the slave processors 12 and 13 has been completed, and access to other processors becomes possible.

By the way, during normal operation, if a failure occurs in the slave processor, for example, the microprocessor 12a resets the slave flip-flop 12b. As a result, the slave flip-flop 12b sends an inactive signal and the driver 1
2c drives the slave ready line 14c inactive. As a result, in the master processor 11, the receiver 11d controls the microprocessor 11a.
recognizes that the slave ready line 14c has become inactive. In other words, it is recognized that a failure has occurred in the slave processor 12 or 13. Similarly, the slave processor 13 also recognizes that a failure has occurred in the slave processor 12.

[0022]

As explained above, in the present invention, a master processor and a slave processor are connected by a master ready line and a slave ready line, and the operating status of the master processor and slave processor is transmitted to the master ready line and slave ready line, respectively. Since the data is essentially transmitted, the operating status of the master processor and slave processors can be immediately recognized, and as a result, the slave processors can be started up appropriately, and load completion and failure detection can be performed immediately. This has the effect of being able to be recognized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention.

[Explanation of symbols]

11 Master processor 12 Slave processor 13 Slave processor 14 Common bus 15 I/O bus 16 I/O control device 17 Memory

Claims (3)

[Claims] Claim 1: An information processing device in which a master processor and a slave processor are interconnected, comprising:
The master processor and the slave processor are further interconnected by first and second control lines, and the master processor has a first control line that sends a master operating status as a master operating status signal to the first control line. and a first monitoring means for monitoring the second control line; An information processing apparatus comprising: a sending means; and a second monitoring means for monitoring the first and second control lines. 2. The information processing device according to claim 1, wherein the master processor and the slave processor are connected by a common bus line, and the first and second control lines are connected to the common bus line. An information processing device comprising: 3. The information processing apparatus according to claim 1, wherein the first and second sending means substantially transmit the information to the master by activating the first and second control lines, respectively. An information processing device characterized in that it transmits an operating state signal and the slave state signal.