JPS63231555A - I/o interface resetting system - Google Patents

Abstract

PURPOSE:To prevent an I/O interface from generating a hang-up state even when input voltage is abnormal by detecting the abnormality of voltage based on the monitoring of an input voltage to a computer and generating a reset signal during the period that voltage impression to a using element is guaranteed. CONSTITUTION:An I/O interface permission signal 9 is '0' when a power supply to a processing part of the computer is OFF, and when the processing part is stabilized at an initial value after turning on the power supply, is turned to '1'. At the start of a power supply disconnection sequence, the signal 9 is turned to '0' again. When instantaneous power failure is detected by a power supply control part during the operation of a system, the signal 9 is turned to '0' to reset an I/O interface. Consequently, the I/O interface can be prevented from generating its hang-up state due to the failure of guarantee of logical operation because of the instantaneous power failure of the input voltage to the computer.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to IO interface control of a computer,
Regarding the reset method.

[Conventional technology]

In conventional devices, as described in Japanese Patent Application Laid-Open No. 56-8296, various circuits have been devised to detect the hang-up state of channels in the computer, but the voltage required to operate the device drops and the hang-up state occurs. There was no way to become one.

[Problem that the invention seeks to solve]

In the prior art, a method has been considered in which when a hang-up state of an IO interface of a computer occurs, this is detected and the hang-up state is avoided.

These are based on the assumption that the detection circuit and the circuit for avoiding the condition operate normally.
A hang-up condition of the O interface cannot be avoided. When a hang-up condition occurs on an IO interface, all IOs on the interface become unusable.

If one IO is connected to multiple computers through an IO interface and is being used in a shared manner, if the IO interface hangs up and the IO becomes hung up, the entire system may go down, resulting in a serious accident. Become.

The purpose of the present invention is to provide IO even when the input voltage of a computer is abnormal.
The purpose is to provide a means to avoid an interface hang-up state.

[Means for solving problems]

The above object is achieved by monitoring the input terminals of the computer to detect voltage abnormalities and issuing a reset signal while the supply voltage to the used elements is guaranteed.

[Effect]

In other words, by detecting an abnormality in the input voltage of the computer and seeing that the condition does not recover for a certain period of time, it predicts that the power cannot be supplied to the preemptive element and sends a signal to the IO interface reset circuit. . I
The IO interface reset circuit puts the IO interface into a reset state before the power supply reaches a voltage that would cause malfunction of the IO interface, thereby avoiding a hang-up state.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1.
2.3 are the channel device and SVP inside the computer, respectively.
(Service Processor), which indicates an ILE source device. The channel consists of 6 channel logic units, 5 channel interface drivers, and 4 IO interfaces. Here, in order to simplify the explanation, the IO interface is explained using only four outputs, but in reality, there are many inputs and outputs. In SVP 2, only the parts related to the present invention are shown. This SVP also performs power control of the computer main body. It is not possible to predict what will be output on the IO interface during the power-up process. Therefore, when the computer is turned on and off,
To prevent uncertain state of IO interface, SVP
It has a power-on completion flip-flop 7 inside. s
For vP, first set this FF to OFF, after the power has been turned on, and after the computer main body and channel section have been set to their initial values.
Turn on 7. 7 is turned on, the IO interface output permission signal 9 is turned on through the OR gate 8.

In this state, the IO interface signal can be output from the channel. This IO Ink 7 Ace is all about output.”
When Ql, it indicates a reset state. Therefore, when the signal 9 is IQ+, the IO interface is in a reset state and no hang-up state occurs. FIG. 50 shows a part of the power supply device of the computer. 10 indicates an input voltage, and 11 indicates an input voltage monitoring circuit. This circuit monitors the input voltage and
When the voltage state below the specified voltage continues for a certain period of time, a power failure detection signal 12 is output. The fixed period of time mentioned here refers to the period of time during which the capacitor of the power supply device can guarantee the output when the human power is temporarily lost. In other words, when the power supply cannot be guaranteed any longer, 12 is output.

12 is connected to the OR gate 8. Therefore, when 12 is output, 9 becomes 0° and the IO interface is reset.

To summarize the above, the IO interface permission signal is at 0 degrees when the computer processing section is powered off, and becomes 11 degrees when it is stabilized at the initial value after the power is turned on. Thereafter, it becomes 0 again at the beginning of the power-off sequence. Furthermore, if a momentary power outage is detected in the power supply control unit during operation, the IO interface permission signal becomes 0° and the IO interface is reset to avoid a hang-up state of the IO interface.

[Effects of the Invention] According to the present invention, it is possible to avoid a situation in which the logic operation cannot be guaranteed due to a momentary power outage of the input voltage to the computer, and the IO interface becomes in a hang-up state.

[Brief explanation of drawings]

FIG. 1 shows a channel device in a computer according to an embodiment of the present invention.
FIG. 3 is a circuit diagram showing the connection between the svp and the power supply device. 1... Channel device. 3...Power supply device. 5... Driver gate. 6...Channel logic section. 7...Power-on completion flip-flop. 8...or gate. 10... Computer input voltage. 11...Input voltage monitoring circuit. 12... Power outage detection signal.

Claims (1)

[Claims] 1. In an electronic computer device, an IO interface controlled by a computer channel, a voltage monitoring circuit that monitors the input power supply voltage supplied to the computer and detects a voltage drop, and the voltage monitoring circuit detects a voltage drop. When detected, it has a timer that starts counting and outputs a signal before the output voltage of the power supply becomes abnormal, and the IO interface can instruct all connected IOs to reset by turning off the output driver. By connecting the output signal of the timer and the output driver of the IO interface, when the input voltage becomes abnormal, after a certain period of time counted by the timer, the driver of the IO interface is turned off and connected to the IO interface. An IO interface reset method characterized by applying a reset to all IOs.