JPS59200357A - Watchdog timer circuit - Google Patents

Abstract

PURPOSE:To attain the automatic monitor even in an initial program loading mode and an initial processing mode by setting the initial value of a counter with an initial value setting fixed memory. CONSTITUTION:A selector SEL selects the data 2 of an initial value setting fixed memory DIP and the data 1 for operation program. In a power-on mode the data 2, i.e., the contents of the memory DIP is selected by the selector SEL and set to a counter as the initial value to give the monitoring during initial program loading and initial processing. When the operation program is executed, the data 1 given by a timer value setting instruction is selected by the SEL and set to the counter.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a watchdog timer circuit that can easily monitor initial program loading and initial program processing time.

(Background Art) A conventional watchdog timer circuit performs its operation only during an operational program.

A watchdog timer circuit having such a configuration is shown in FIG. 2 in FIG. 1, the counter is an own counter that can be read/written by a program, and the WDT (watchdog timer) clock is a watchdog timer clock generation circuit.

The counter of FIG. 1 operates as follows.

Data 1 is set in the counter from the bus, and the counter value is sequentially decremented by the WDT clock.

For example, the explanation will be given with reference to FIG. In the part marked with note (1) in FIG. 2, the IPL operation and initial processing can be completed.

When data 1 is set in the counter, the counter is incremented by the clock, and when data 1 is set again, the counter value returns to the initial value and the counter is down. Further, if data 1 is not set in the counter until the counter value II O11 is reached due to some abnormality, an alarm is generated as a watchdog timer error.

Problems with this configuration will be explained using FIG. 3.

FIG. 3(b) shows a watchdog timer counter. The watchdog timer counter does not operate during the initial program loading and initial processing after PGvVERON, but starts operating after completion, so it is monitored only during the operational program. When a malfunction occurs during initial program loading and initial processing, the watchdog timer function is not operating, so no abnormality is notified.

Therefore, if there is no human intervention, the device will remain in an abnormal state, and the device will not be able to fulfill its own role. There is also a drawback that humans have to monitor the equipment.

(Problem of the Invention) The present invention has been made to solve the above-mentioned problems, and will be described in detail below.

(Structure and operation of the invention) FIG. 4 shows an example of the structure of the invention, and FIG. 5 shows a time chart.

In FIG. 4, DIP is a fixed memory for initial value setting. SEL is a selector and I': 1 data 2 by DIP
and select data 1 for the operational program. The pond is the same as the conventional method.

The operating method will be explained using FIG. Note (
In part 1), IPL operation and initial processing are executed.

Data 2, which is the contents of DIP, is set to SE when power is turned on.
When the initial program is selected by L and set as an initial value in the counter, the time of initial processing is monitored. After the operation program starts running, data 1 given by the timer value set command is set as an initial value in the counter selected by SEL.

(Effects of the Invention) As described above, since initial values can be set using DIP, automatic monitoring can be performed during initial program loading and initial processing, and it is also easy to take measures when an abnormality occurs.

This also has the advantage of not requiring constant human intervention and monitoring.

The present invention is widely applicable to microcomputer-applied devices and is extremely effective for unmanned monitoring.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a conventional watchdog timer, Figure 2
The diagram shows watchdog timer counter operation - number of sections, number 3
FIG. 4 is a block diagram showing an example of the watchdog timer of the present invention, and FIG. 5 is an operation time chart of the watchdog timer of the present invention. 1 Counter: Counter for WDT 2 DIS, Fixed memory 3 SEL', : Selector Patent applicant Oki Electric Industry Co., Ltd. Patent agent Megumi Yamamoto -

Claims (1)

[Claims] This is a timer for detecting that the conbeater program has fallen into an abnormal loop.When a certain period of time elapses, an interrupt is generated and the program is in a normal state.If the program is in a normal state, by resetting the interrupt, an alarm is issued when the program is in an abnormal state. will occur.
The watchdog timer includes a fixed memory for setting the initial program load and initial processing time, a timer value setting circuit for resetting by command within a certain period of time during the program, and a timer value setting circuit for setting the data in the fixed memory and the timer value setting circuit. A watchdog characterized in that it has a selector that selects data and a watchdog timer counter that sets the output signal of the selector and counts with a dimming pulse, and is capable of monitoring initial program loading, initial program processing, and operation program. timer circuit.゛=Yodonromi