JPS62285155A - Address array device - Google Patents

Abstract

PURPOSE:To omit the interruption of processing due to a fault detected in a partial cancel mode by forcibly making an ID part and space identifier coincident by a comparator for partial cancel processing when said fault is detected. CONSTITUTION:An address reading out an address conversion buffer memory TLB102 is set to an address register 101 and are entry of the TLB102 is read out. The ID part read out of the TLB102 is compared with the space identifier 109 by the comparator 103. Then prescribed TLB cancel processing is performed if coincidence is obtained from said comparison. While both LA and PA parts are also read out when the TLB102 is read out and fault detecting circuits 104-106 detect the faults of each part. If a fault is detected, the faulty entry is cancelled regardless of the decision of the comparator 103.

Description

[Detailed Description of the Invention] 5. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an address array device, and particularly to an address array device for efficiently handling failures during partial cancellation processing of the address array device. Regarding a preferred address playing device.

[Conventional technology]

In recent years, various remedies for common AM failures have been taken, one of which is the use of a buffer memory address array (BAA), which is a type of address play, as described in Japanese Patent Laid-Open No. 55-87652. There is something for obstacles. This is the BA when accessing the buffer storage (BS).
If a BAA failure is detected when indexing A, there is no entry that should be forcibly accessed (this is called not in B).
S), new data is transferred from the main memory (MS) to the BS, and a new address is stored in the failed BAAK. However, B.S.
Also, the case where a failure of the BAA is detected when partially canceling the BAA was not considered. The partial cancellation process is a process of canceling and invalidating only the IJ when the target address exists in the BAA.

[Problem that the invention seeks to solve]

The purpose of the present invention is to prevent the processing itself from being interrupted (allowing it to continue) by subjecting it to partial cancellation in response to a fault in the data read from the address array Vcttitt that occurs during the partial cancellation processing of the address play device. It is to do so.

[Means for solving problems]

The above object is achieved by forcibly determining a match when @ harm is detected when the comparison circuit in the partial cancellation process determines whether the comparison circuit matches or does not match.

[Effect]

When a failure in the address play device is detected during partial cancellation processing in the address array device, the comparator circuit for partial cancellation processing is forced to match, thereby canceling the entry as a target for partial cancellation. There is no need to interrupt processing due to failure.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows an address translation buffer storage (hereinafter abbreviated as TLB) that stores logical addresses and real addresses corresponding to the logical addresses, which is one of the address play devices. This example shows partial cancellation of the ID portion of the TLB.

FIG. 2 shows the ID part in the TLB, which is an index for identifying multiple virtual spaces, and a 4-bit space identifier can identify up to 16 spaces. Furthermore, it has an Ebit (inno (ridpid)) indicating whether the correspondence between the logical address and the real address of this entry is valid or not, and a parity of the ID part, and consists of a total of 6 bits. , the space identifier to be evicted is determined according to the eviction algorithm.This eviction is performed by sequentially reading all entries in the TLB and comparing them with the space identifier to be evicted.If they match, the ebit of the ID part of that entry is set. 1 is achieved by eliminating the entry of the space identifier to be evicted from the TLB.

Returning to FIG. 1, the TLB 102 is set in the address register 101.
1 of TLB 102 is set.
Read the entry. I read from TLH102
The part 1) is compared with the space identifier 109 by the comparator 103, and if they match, it passes through the OR gate 107, passes through the cancellation request line 120, and undergoes a predetermined TLB cancellation process (not shown). -Also, if the comparison in the comparator 103 is a mismatch, the match signal to the OR gate 107 is not transmitted. When TLB102 is read, the ID section and the L
Part A and part PA are also read out. These read data are subjected to failure detection circuits (parity check in this example) 104, 105 and 106 at the same time as comparison of the ID part to detect failures in each part. If any one or more of the fault detection circuits detects a fault, it is transmitted to the OR gate 107 without depending on the judgment of the comparator 103, and is transmitted to the cancellation request line 120, so that the fault entry is canceled.

[Effects of the Invention] According to the present invention, TLB failure during partial cancellation processing can be avoided.
It is characterized by the fact that it can be processed without causing a failure, and has the effect of eliminating the interruption of partial cancellation processing due to a failure or the loss of time required for subsequent failure processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of partial cancellation of the TLH according to an embodiment of the present invention, and FIG. 2 is a detailed diagram of the ID section of the TLB of FIG. 1. 102...TLB, 103...IL) m
f) Comparators, 104-107...fault detectors, 107
．．・, or gate.・)

Claims (1)

[Claims] 1. In an address array device that stores a plurality of addresses and is equipped with a comparison circuit for comparing the stored address and the address to be partially canceled, if an error occurs in the address read from the address array device during partial cancellation processing. An address array device characterized in that when detected, the output of the comparison circuit is forced to match.