JPS62237551A - Microcomputer device - Google Patents

Abstract

PURPOSE:To omit a parity checking ROM for a ROM by sequentially reading out all memories, writing a parity bit in a parity RAM every address and writing the information of an unloaded area in a memory loading state display memory. CONSTITUTION:When power ON is detected by a power ON detector 6, an MPU 1 reads out addresses corresponding to all memory spaces to be loaded sequentially, forms parity bits by a parity checker generator 11 and stores the parity bits in the RAM 3. Then, the MPU 1 writes/reads out data in/from memory spaces successively to decide whether the memory is a ROM, a RAM or an unloaded memory. In case of the unloaded memory, a memory state display bit is written in a loading state display ROM 4 and the parity bit to be an error is written in the parity RAM 3. Consequently, a parity check ROM for the memory space constituted of the ROM can be omitted and a parity check error can be detected from a memory unloaded area without fail.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer device having a ROM as a memory, and particularly to a microcomputer device suitable for checking data in the memory.

[Conventional technology]

To check the data of a microcomputer device having a ROM as a conventional memory, 1, for example,
As shown in Publication No.-108944.

When the power is turned on, the address generation circuit generates an address corresponding to the data in the ROM, the upstream parity generator generates a parity bit based on the data pattern from the ROM, and this parity bit is stored in the RAM. Therefore, from then on, the data of ROl'1 was subjected to a parity check.

[Problem that the invention seeks to solve]

In the data check of the prior art described in 1-, the parity bit is generated based on the data pattern of the ROM, so the memory space is limited to the mounting area of the ROM.

If the data check of the prior art is applied to all areas of the memory space, it will not be possible to check the data in the area where memory elements are not installed, or the rung 11 pattern of the area where memory is not installed (regular non-memory area). Since the parity pattern 1- is generated by the pattern al, l"1"), there is a problem that a parity error does not occur even if the pattern is [-z memory non-implemented].

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor device 7 that can perform a parity check by generating and storing parity bits that can be checked for parity in all areas of a memory space based on a pattern of memory elements.

[Means for solving problems]

For the above-mentioned area, the information that the memory is not installed is read out for each address (data A), IF read (data T3), and data C is read out instantly. ), and finally read it again after some time (data ■)).

The problem is solved by comparing and obtaining those data.

[Effect]

, 1. According to the above means, each data has the following relationship, and accordingly, it is detected whether the memory is ROM, RAM, or unimplemented. That is, (i) when data A=I) and data B≠C, RO
M area.

(it) RAM area when data 13=c=D, (in) memory not implemented when data A=Dand data B=CFll data)3≠1].

It is.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.

FIG. 1 is a hardware configuration diagram showing an embodiment of a microcomputer device according to the present invention.

In Figure 1, ■ is a microprocessor M I')
LJ, 2 is a program memory ROM that stores the program of MPU 1, and has an area where ROM and RAM of memory elements are mounted and an area where no memory elements are mounted in the entire memory space. 3 is a parity memory RAM that stores a parity bit according to the data of each memory at 1nos in an address corresponding to each memory address for checking the data of ROM2, and 4 is a parity memory RAM in which a memory element is mounted at each memory address of ROM2. This is a mounting status display memory RAM that stores mounting status information at an address corresponding to each memory address.

5 is the MR (memory read) signal 1a of M P tJ 1
RAM MR (memory read) M number 5a or R
AM MW (merit rewrite) signal 5b and DATA
CT[, RAM WRFrE CTL (write control) circuit that outputs (data control) signal 5c, is a power-on (POWERON) detector %7 is a manual signal generator (MANuAl, ), 8 is RAMwl ( TTI'! The data bus 15 and the data bus 1 are separated from the signal 5cl of CT1.5, and a data pattern in which M TJ U 1 becomes a no-operation on the data bus 18 (command word that does not involve execution: skip) DATA CTL to forcefully output
In the (data control) circuit, 9 generates a “0” data pattern, which is a no-operation in this case.
O″GEN (generator).

10 is an address decoder (ADD) that sequentially decodes the addresses of all the memory spaces of ROM2 using the address bus.
RDF! (1:0 DE). 11 is a parity checker generator (PTY CH[E
CK GEN), and 12 is a memory mounting detection circuit (MOUNT DET) that detects whether the memory element is ROM or RAM, or whether the memory element is not mounted, according to the data output from the ROM2. 13 is a parity error detection circuit (PTY ERRDFT), and 14 is an error processing circuit (ERR). 15 is a data bus, 16
is an address bus, 17 is an OR gate, and 18 is a data bus.

Figure 2 shows Figure 1 (7) RAM wRITE CTL5
(7) Detailed configuration side view. In FIG. 2, 20 is a flip-flop (FF), 21 is a delay circuit, and 22 is an EX
-OR circuit, 23 is a NAND circuit, 24.25 is an inverter circuit, 26 is a tri-state gate circuit, and 27 is a pull-up (pu+, t, up) resistor. Third
The diagram is the RAM shown in Figure 2. This is a time chart of CTL5 white signal. Figure 4 shows the DATA C of Figure 1.
It is a detailed elliptical example diagram of TL8. In FIG. 4, 41.
42 is an inverter circuit%43.44 is a NAND circuit, 4
5°46.47 is a tri-state gate circuit.

FIG. 5 shows ROM2. of FIG. FIG. 4 is a conceptual diagram showing an example of a memory configuration of RAM 3.4. In FIG. 5, RO of memory elements in the entire memory space (addresses 0 to N) of ROM2 is shown.
It has an area where M and RAM are mounted, and a non-memory area where neither ROM nor RAM of the memory element is mounted. In other words, in ROM2, there is an area where no memory element ROM-bRAM exists as an area where memory is not installed, but assuming that there are sockets or terminals on the circuit, it is assumed that neither ROM nor RAM is mounted in the socket etc. It is. FIG. 6 is a time chart for determining whether the ROM2 of the memory mounting detection circuit 12 of FIG. 1 is ROM, RAM, or an unmounted area. Further, FIG. 7 is a flowchart explaining the operation of FIG. 1.

Now, when the microprocessor device shown in FIG. 1 is powered on, a detection signal 6a from the power-on (POVERON) detector 6 or a manual signal generator
(MANUAI,) 7Nor signal 7a is OR gate 1
RAM WRTTEeT via signal 17a via 7
I, 5 Tell them. RAM wRITIE CTL5
processes the MR (memory read) signal 1a output by the MPUI, which starts operating when the power is turned on, as follows.

(7) RAM IIRITE CTL5 power-on signal 17a is latched to FF20, I) AT
A CTC signal 5C is output. The MR (MR) signal 1a from one MPUI is converted into an I(AM MR (RAM MR) signal 5a as it is, or is processed and sent to the RAM sv (ii
^M M%1) It is determined whether the signal will be 5b. At this time, the inverter circuit 25. The I(AM MR signal 5a and the RAM Mld signal 5b are always selected by a circuit such as the pull-up resistor 27. The RAM M%l signal 5b is connected to the delay circuit 21. EX-OR circuit 22. By the NAND circuit 23, as shown in FIG.
) RAM WRITE CTL5 In the white signal time chart, ■ from MPU1 like the RAM M1m signal.
Processing is performed so that the trailing edge of the RAM MW multiplied signal rises a time T earlier than the trailing edge of the signal 1a.

The time chart of the RAM WRITE CTL5 white signal in Fig. 3 shows that after power-on (POVHRON), the MR (MR) signal from MPU1 is input to the RAM WRITE CTL5 white signal.
AMAR) signal 5a or RAM MW (RAM M
ll) Timing of signal 5 b d conversion and address decoder (ADDRDRCODF) 10 in FIG.
1EAD to RAM3 and 4 by signal 10a from
(IJ-do) The timing at which the WRITE mode is controlled is shown.

The mode in which RAS information is now written to RAM (RAM
In the WRITE-11-- mode, see Figure 1 +7) MPUI
ROM2 is read by the MR signal 1a outputted when the ROM2 starts operating, and MPUL reads addresses corresponding to the entire addressable memory space of ROM2, starting from address O and following the addresses on the address bus 16 that are sequentially outputted. The contents of the stored memory are output to the data bus 15.

Depending on the pattern of this output data, the parity checker generator (PTI/CHECK GEN)
11 generates a parity bit. On the other hand, M
The MR signal 1a output from PU1- is the RAM W
RITE CT1.5 Double processed Sareta RAM W
It is input as the RITE signal Lb to RAM3&,-. As a result, the parity bit from the above parity checker/generator 11 is stored in RAM:3.

When writing parity bits to parity RAM3 according to the data pattern of ROM2, DATA
CTL8 is RAM WRITE! CTL5 (7)
The signal 5c disconnects the data bus 15 and the data bus 18, and forcibly outputs a data pattern to the data bus 18 in which MPU 1 becomes a no-operation.

In Figure 4, DATA CTI, 8, data bus 1.5,
Showing one circuit of 1.8, Tite, RA
M WRITE CTL 5 DATA (: Forced by control of TL signal 5c II OIIG E N 9
The "'0" data pattern generated in the data bus 18-
Flow to H. As a result, the MPUL detects a no-operation instruction, advances the address to 1, and outputs the MR multiplication signal a again in order to read the next address in the ROM 2 without executing it. In this way, ROM2 is
When all addresses of all memory spaces have been output, parity bit information is stored in the parity RAM 3 for all memory spaces.

Next, the address decoder 10 decodes the final address of the entire memory space of the ROM 2 from the address bus 16,
Signal 1. Oa allows RAM l+1RITl'! C
Tell TL5. As a result, (Figure 2) RAM 1iil
(Switch the state of FF20 of ITF CTL5 and
By controlling the TA and CTL signals 5c, the MPU
MR signal 1a of I to RAM WRITE CTL5
to the RAM 3.4 as the RAM MR signal 5a. Also, DAT from RAM WRITE CTL5
A CTL signal 5c causes the opening ^TACTL8 in Fig. 4 to
connects data bus 15 and data bus 18.

Now, in the RAM read-only mode (RAM READ mode) after performing the above signal switching, the MPU 1 again uses the MR signal 1a to sequentially output addresses corresponding to the entire memory space of the ROM 2, starting from address 0. According to the addresses on the address bus 16, the microprogram repeatedly writes and reads all addresses in the entire memory space of the ROM 2 at the timing shown in FIG. Based on the comparison, it is determined whether the memory element is ROM or RAM is unmounted by the memory mounting detection circuit (MOUNT D[4T) 12 as follows. That is, ■ First read the contents of the memory for one address and store it as data A), ■ Then write data B other than data A to the memory at the same address and store it as data B), ■ Instantly The contents of the memory at the same address are read out and stored at some time (Data C); (2) The contents of the memory at the same address are read out again after some time (Data D);

As a result, the memory mounting detection circuit 12 determines the memory mounting state using the following relational expression. That is, (i) data A
= ROM mounting area when data B≠C, (it) RAM mounting area when data B = C = D, (fit) data A = D and data R = Ca
nd When data B≠D, the memory is not installed area. (nRnd#P is the AND condition of logical product).

Note that the above relational expression utilizes the characteristic (principle of dynamic RAM) that data B written in step (3) is temporarily stored by stray capacitance in areas where no memory is installed.

In other words, as a characteristic of the non-memory area, the memory element, either ROM or RAM, is not mounted, so it is in an open state in terms of circuitry, but there is a small amount of capacitance such as stray capacitance. Therefore, according to the timing shown in Figure 6,
When data B, which is the above ■, is written to an unimplemented area of the memory, and the same area is immediately read using ■, the data C at that time becomes the data B written in ■ due to the electric charge stored in the capacitance such as stray capacitance. The pattern can be read (data B=C). However, even if the same area is read after some time in ■, the data D at that time is the charge stored in the capacitance such as stray capacitance, so the pattern of data B written in ■ disappears and cannot be read. No (usually all “1”) (pattern B≠D). Thus, the relational expression for determining whether the above memory element is ROM, RAM, or unmounted is (i) In the case of a ROM mounting area, data A =
D (ROM read data remains unchanged) and data B#C
(Writing to ROM is not possible). (u) In the case of the RAM mounting area, data B = C = D (data written to RAM has the same pattern as the written data whether it is read immediately or after some time), and (
in) In the case of an area with no memory installed, data A = D = fixed pattern (the data read out after a period of time has stabilized is the normal fixed pattern all “1” because no memory is installed)
''), and data B=C and data B≠D (depending on the characteristics of the unimplemented area).

As a result of the above, the memory mounting detection circuit 12 detects whether the memory area is the ROM mounting area or not for the entire memory space of ROM2.
When it detects whether it is an M-mounted area or a non-memory-mounted area, it stores memory state display bits indicating the memory state in the memory-mounted state display ROM4, and detects a parity error in the parity RAM3 for the address of the non-memory-mounted area. A parity bit like this is written by the parity checker/generator 11.

Then run the normal program and write the parity RAM
The parity checker/generator 11 compares the output data 3a of 3, the output data 4a of the memory mounting state display RAM4, and the output data pattern of ROM2.
■ If a parity error occurs in the memory implementation area.

■ When an address in a non-implemented area of memory is accessed, the parity error detection circuit (PTYE) is activated by the signal 11a of the parity checker/generator 11.
RRDF! Data is input to T) l 3 and is further transmitted to the error processing circuit (F:RR) 14 for parity error processing.

As described above, according to this embodiment, in the parity check of the memory of a device equipped with a microcomputer (a microcomputer device! 1-bit parity RAM that generates parity bits based on patterns and corresponds to memory addresses
At the same time, for unimplemented memory areas, information indicating that they are unimplemented is written to the 1-bit memory implementation status display memory, thereby eliminating the need for a parity check ROM for the memory space composed of ROM, and reducing the memory Parity check errors must be detected for unimplemented areas.

〔Effect of the invention〕

As described above, according to the present invention, there is no need for a parity check T< OM for the memory space constituted by the ROM of a microcomputer device, and parity check errors can always be detected in areas where no memory is implemented. Become.

[Brief explanation of drawings]

FIG. 1 is a hardware configuration diagram showing an embodiment of a microcomputer device according to the present invention, and FIG. 2 is a diagram showing the RA of FIG. 1.
Detailed configuration diagram of the M WRITE control circuit, Figure 3 is the signal time chart in Figure 2, Figure 4 is the DA in Figure 1.
5 is a side view of the memory configuration of the ROM and RAM in FIG. 1, FIG. 6 is a determination time chart of the memory mounting detection circuit in FIG. 1, and FIG. 7 is a detailed diagram of the TA control circuit. It is an operation flowchart. 1...MP tJ, 2...ROM, 3...Parity RAM. 4...Mounting status display memory, 5...RAM WRT
TF, control circuit, 6... power-on detector,
8...1]^TA control circuit, 9...lj
OP1 generation circuit, 10...address decoder, 11.
...Parity checker generator, 12...Memory implementation detection circuit, 1; 3...Parity error detection circuit, 14...Error processing circuit.

Claims (1)

[Claims] 1. ROM and RAM as memories, and the ROM and RAM
A microcomputer device having a check data memory storing check data for checking the data of M includes an address generation circuit that sequentially generates addresses corresponding to all addressable memory areas, and an address generation circuit that sequentially generates addresses corresponding to all addressable memory areas, and A circuit that operates based on timing to control reading and writing of the memory, a check data generation circuit that generates check data according to data output from the memory, and a check data RAM that stores the data generated from the check data generation circuit. and means for detecting whether the memory is ROM, RAM, or non-implemented, and based on the check data from the check data RAM and the detection information from the means for detecting whether the memory is ROM, RAM, or non-mounted, the data in the memory is A microcomputer device characterized by checking. 2. The microcontroller according to claim 1, wherein the means for detecting whether the memory is a ROM, a RAM, or a non-implemented memory is detected by repeatedly writing and reading the memory and comparing respective data patterns. computer equipment. 3. Detection by repeating the writing and reading of the memory and comparing each data pattern is to first read and store the data for one address and store it as data A, then write data other than data A to the same address. Write it as data B, instantaneously read and store the same address as data C, read the same address again after some time as data D, and write data A and B respectively.
3. The microcomputer device according to claim 2, wherein the microcomputer device performs the determination by comparing data C and data D.