WO2016042751A1

WO2016042751A1 - Memory diagnosis circuit

Info

Publication number: WO2016042751A1
Application number: PCT/JP2015/004656
Authority: WO
Inventors: 一心松尾; 等黒柳
Original assignee: 株式会社デンソー
Priority date: 2014-09-16
Filing date: 2015-09-14
Publication date: 2016-03-24

Abstract

In the present invention, a memory diagnosis circuit is provided with the following: an error detection and correction circuit (3) that performs error detection of N (N is a natural number of 2 or greater) bits or more and error correction of (N-1) bits or less for data which is read from a memory (2, 11); a first data buffer (5) in which is held the data that was error corrected by the error detection and correction circuit; a second data buffer (6) in which the data is directly held; a comparator (7) that compares the data values held in the first and second data buffers; and an error detection and correction monitoring circuit (8, 9). In the error detection and correction monitoring circuit, on the basis of the comparison results of the comparator, the data value held in the first data buffer is validated. Or, in the error detection and correction monitoring circuit, the data value held in the first data buffer is invalidated, and an abnormal signal is output.

Description

Memory diagnostic circuit

Cross-reference of related applications

This application is based on Japanese Patent Application No. 2014-187659 filed on September 16, 2014 and Japanese Patent Application No. 2015-99035 filed on May 14, 2015. The description is incorporated.

The present disclosure relates to a memory diagnostic circuit including an error detection correction circuit that performs error detection and error correction processing on data read after being written to a memory.

For example, when a memory such as a DRAM is used, an error detection and correction (ECC) circuit is provided to improve data reliability. The error detection and correction circuit has a function of detecting and correcting an error in data read from the memory. However, taking into consideration the possibility that a failure will occur in the error detection and correction circuit itself, a countermeasure is required. For example, in Patent Document 1, the memory and the error detection circuit are all duplicated, and the detection results of the two error detection circuits are compared to select which memory side data is used to improve reliability. The microcomputer which aimed at is disclosed.

However, as in Patent Document 1, the configuration in which everything is duplicated is redundant, and it is inevitable that the size of the system increases and the cost increases.

JP 2004-5627 A

This disclosure provides a memory diagnostic circuit that can detect a failure of an error detection and correction circuit with a simpler configuration.

In one aspect of the present disclosure, the memory diagnostic circuit includes an error detection and correction circuit that performs error detection of N bits or more and error correction of (N−1) bits or less with respect to data read after being written to the memory, and the memory A first data buffer that stores data read from the memory and error-corrected by the error detection and correction circuit; a second data buffer that directly stores data read from the memory; and the first data buffer And a comparator for comparing data values respectively stored in the second data buffer, and an error detection / correction monitoring circuit. In the error detection / correction monitoring circuit, when both data values differ by (N−1) bits or less in the comparison result of the comparator and the error detection / correction circuit performs error correction, the data is stored in the first data buffer. I) whether both data values differ by (N−1) bits or less in the comparison result of the comparator and the error detection / correction circuit does not perform error correction, ii) or both The data value of N is not different by (N-1) bits or less, but it is confirmed whether the error detection / correction circuit has corrected the error, or iii) whether both data values are different by N bits or more in the comparison result of the comparator When confirmed, or iv) When the error detection / correction circuit confirms that an error is detected, the data value stored in the first data buffer is invalidated and an abnormal signal is output.The N is a natural number of 2 or more.

Thus, by comparing the data values stored in the two data buffers with the comparator, it is possible to easily determine whether there is an abnormality in the error detection / correction circuit.

The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description with reference to the accompanying drawings. The drawing
FIG. 1 is a functional block diagram illustrating a configuration of a memory diagnostic circuit according to a first embodiment of the present disclosure. FIG. 2 is a functional block diagram illustrating a configuration of the memory diagnostic circuit according to the second embodiment of the present disclosure, and is a diagram illustrating a state of each signal when the CPU reads the second check data. FIG. 3 is a diagram illustrating a state of each signal when the CPU reads the first check data, and FIG. 4 is a diagram illustrating a state of each signal when the CPU reads the first check data having an error in the ECC bit.

(First embodiment)
As shown in FIG. 1, the memory diagnostic circuit 1 of this embodiment is disposed between a memory 2 and a CPU (not shown). The memory 2 is, for example, a DRAM, SRAM, EEPROM, flash ROM, or the like. The memory diagnostic circuit 1 includes an ECC circuit 3 as an error detection / correction circuit. When the CPU performs write access to the memory 2, the ECC circuit 3 generates a plurality of ECC bits as error detection data based on the write data, and writes the ECC bits together with the write data. When the CPU performs read access to the memory 2, the ECC circuit 3 reads ECC bits together with data from the memory 2, performs a predetermined logical operation on the read data and the ECC bits, and performs N (≧ 2) bits or more. Error detection (error) and error correction of (N-1) bits or less are performed. In the following description, it is assumed that N = 2.

The error / correction result output unit 4 outputs a signal indicating whether 1-bit error correction or 2-bit error detection has been performed from the value of the ECC bit read when the CPU performs read access. . When the CPU performs read access to the memory 2, data read from the memory 2 as detection and correction target data is read through the ECC circuit 3 as described above, and is used as the BUF 1 as the first data buffer. 5 is stored. When the ECC circuit 3 detects a 1-bit error, the error-corrected data is stored in the first data buffer 5. Then, the CPU reads the data once stored in the first data buffer 5.

Further, the data read from the memory 2 at the time of read access is simultaneously stored directly in the second data buffer 6 as the BUF 2 without passing through the ECC circuit 3. Data stored in the first and

second data buffers

5 and 6 is input to the comparator 7 as a magnitude comparator. The comparator 7 compares the two input data, and if there is an error of 1 bit, outputs a high level signal to one input terminal of the EXOR gate 8 as a part of error detection and correction (ECC) monitoring circuit. . If there is an error of 2 bits or more, the comparator 7 outputs a high level signal (error) to one of the input terminals of the 3-input OR gate 9 as a part of the ECC monitoring circuit.

The error / correction result output unit 4 outputs a high level signal to the other input terminal of the EXOR gate 8 when the ECC circuit 3 performs 1-bit error correction. The error / correction result output unit 4 outputs a high level signal to the other input terminal of the OR gate 9 when the ECC circuit 3 detects an error of 2 bits or more. The other input terminal of the OR gate 9 is connected to the output terminal of the EXOR gate 8.

The output terminal of the OR gate 9 is connected to one of the input terminals of the AND gate 10. The other input terminal of the AND gate 10 is supplied with a signal for controlling the signal output from the AND gate 10 by the CPU writing to a register (not shown). The control signal is set to a high level (H) when the microcomputer including the CPU, the memory diagnostic circuit 1 and the memory 2 normally operates. The case where the control signal is set to the low level (L) (when the function is checked) will be described in the second embodiment. When the output signal of the AND gate 10 becomes a high level, it becomes an abnormality detection signal indicating that the ECC circuit 3 has an abnormality. For example, it becomes a signal (RESET) for resetting the microcomputer, or an abnormality is detected with respect to the host control device. The signal is used to notify detection.

Next, the operation of this embodiment will be described. When the CPU performs a read access to the memory 2, the read data is stored in the first data buffer 5 through the error correction process by the ECC circuit 3 and also stored in the second data buffer 6 as described above. The Then, the comparator 7 compares the data stored in the

data buffers

5 and 6. If there is no error in the data read from the memory 2, the signals output from the comparator 7 and the error / correction result output unit 4 all indicate a low level, so that the output signal of the AND gate 10 also remains at a low level. . The following “normal” and “abnormal” are evaluations related to the operation of the ECC circuit 3.

(A) <Normal: 1 bit error corrected>
When the ECC circuit 3 detects that the data read from the memory 2 has a 1-bit error, the error is corrected, and the corrected data is stored in the first data buffer 5. As a result, a difference of 1 bit from the data stored in the second data buffer 6 occurs, so that the comparator 7 outputs a high level signal to the EXOR gate 8. Since the ECC circuit 3 performs the correction process, the error / correction result output unit 4 also outputs a high level signal to the EXOR gate 8. Therefore, the output signal of the EXOR gate 8 becomes low level.

If a period for masking the output signal of the EXOR gate 8 during normal operation is required according to the timing of read access executed by the CPU, the logic for this is placed between the EXOR gate 8 and the OR gate 9. What is necessary is just to add suitably.

(B) <In case of abnormality: 1-bit difference occurs without correction>
On the other hand, there is a 1-bit difference in the data stored in the

data buffers

5 and 6, and the comparator 7 outputs a high level signal to the EXOR gate 8, but the ECC circuit 3 is not performing correction processing. The error / correction result output unit 4 outputs a low level signal. Therefore, the output signal of the EXOR gate 8 becomes high level, the output signal of the AND gate 10 becomes high level via the OR gate 9, and a failure is detected.

In this case, it is highly possible that the value of the data stored in the second data buffer 6 is different from the value of the data read from the memory 2 by the ECC circuit 3, but there is a possibility that the ECC circuit 3 has failed. There is also. Thereby, it is avoided that the CPU reads and uses the data of the first data buffer 5 for which the correctness is not guaranteed.

(C) <In case of abnormality: 1 bit difference with correction>
Contrary to the case of (B), the comparator 7 outputs a low level signal to the EXOR gate 8, but when the ECC circuit 3 performs correction processing, the output signal of the EXOR gate 8 also becomes high level. Therefore, the output signal of the AND gate 10 becomes high level, and a failure is detected. In this case, there is a 1-bit difference between the data stored in the data buffers 5 and 6, but it is assumed that both data match as a result of the ECC circuit 3 performing the correction process.

In addition, since the ECC circuit 3 performs error correction in the same manner even when there is no error in the read data of the CPU and a 1-bit error occurs in the corresponding ECC bit, the state is the same as in the case (C). However, in this case, the data stored in the first data buffer 5 needs to be valid. It can be determined by referring to the ECC bit whether the 1-bit error has occurred in the read data or the ECC bit.

For example, three status bits are generated from the ECC bits, defined as follows, and given to the error / correction result output unit 4.

1st bit: 2 bits or more error → “error” output 2nd bit: 1 bit data error → “correction” output 3rd bit: 1 bit ECC bit error → “correction” output not output Error / correction result output The unit 4 refers to the status bit to determine which of error / correction is output. In the case of (C), since the third bit is set, the signal output to the EXOR gate 8 is kept at the low level.

(D) <Normal: An error of 2 bits or more is detected>
When the ECC circuit 3 detects that the data read from the memory 2 has a 2-bit error, the error / correction result output unit 4 outputs a high level signal (error) to the OR gate 9. Therefore, the output signal of the AND gate 10 becomes a high level, and a failure is detected. Also in this case, it is avoided that the CPU reads and uses the data in the first data buffer 5.

(E) <In case of abnormality: difference of 2 bits or more between both data>
If there is a difference of 2 bits in the data stored in the data buffers 5 and 6, the comparator 7 outputs a high level signal to the OR gate 9. Therefore, the output signal of the AND gate 10 becomes a high level, and a failure is detected. Also in this case, as in the case of (B), the value of the data stored in the second data buffer 6 is different from the value of the data read from the memory 2 by the ECC circuit 3, or the ECC circuit 3 There may be a failure.

As described above, according to the present embodiment, in the memory diagnostic circuit 1, the ECC circuit 3 performs 2-bit or more error detection and 1-bit error correction on data read after being written to the memory 2. Data read from the memory 2 and error-corrected by the ECC circuit 3 is stored in the first data buffer 5, and data read from the memory 2 is directly stored in the second data buffer 6. The comparator 7 compares the data values stored in the first and second data buffers 5 and 6, respectively.

The ECC monitoring circuit composed of the EXOR gate 8 and the OR gate 9 stores in the first data buffer 5 if both data values differ by 1 bit in the comparison result of the comparator 7 and the ECC circuit 3 performs error correction. The data value stored in the first data buffer 5 is invalidated for the abnormal case (B) (C) (E) and the normal case (D) described above. Therefore, it is possible to easily determine whether the ECC circuit 3 is abnormal.

In addition, the error / correction result output unit 4 outputs an EXOR when there is no error in the data stored in the first data buffer 5 and there is a 1-bit error in the ECC bit corresponding to the data and the correction is performed. Mask the gate 8 without outputting the “correction” signal. Accordingly, it is possible to avoid invalidating data stored in the first data buffer 5 without error. In addition, the external logic configuration for that is simplified.

Here, the error / correction result output unit 4 stores and holds the above-described status bits in a register or the like, and after the diagnosis, by reading the status bits held by the upper control device or the like, an “error” , “Correction” can be determined. In addition, it is possible to determine how many error bits are present and whether “error” or “correction” has occurred.

Therefore, for example, when the value of “N” is relatively large, the external control device or the like is operating normally as a result of the error correction of the ECC circuit 3 before the “error” occurs. Can be recognized. As a result, the occurrence of an error at the stage of normal operation before the “failure” occurs as an alarm, and for example, treatment such as replacement of the memory 2 can be performed in advance.

Furthermore, failure analysis can be easily performed by comparing the number of error bits from the status bits. In addition, the error / correction result output unit 4 also holds the bit position corrected by the ECC circuit 3, thereby enabling more detailed failure analysis.

(Second Embodiment)
Hereinafter, the same parts as those of the first embodiment are denoted by the same reference numerals, description thereof is omitted, and different parts will be described. As shown in FIG. 2, in the second embodiment, a check data storage area 12 is provided in a memory 11 that replaces the memory 2. The check data storage area 12 stores first and second check data in advance. These first and second check data are used when executing a check sequence for confirming whether the function of the ECC circuit 3 is normal or not when the system including the memory diagnostic circuit 1 is activated. .

The first check data is set to a combination in which read data and ECC bits indicate a 1-bit error, and the second check data is set to a combination in which both indicate an error of 2 bits or more. Further, in this case, the CPU sets one of the input terminals of the AND gate 10 as a low level as a part of the ECC monitoring circuit to prevent the reset signal from being output.

As shown in FIG. 2, when the CPU reads the second check data, the data stored in the first and second data buffers 5 and 6 match, but if the ECC circuit 3 is normal, an error / correction result is obtained. The output unit 4 outputs “error”. Therefore, the output signal of the OR gate 9 becomes high level.

As shown in FIG. 3, when the CPU reads the first check data, if the ECC circuit 3 is normal, a 1-bit error is detected and corrected, so the error / correction result output unit 4 outputs “correction”. . The comparator 7 detects a 1-bit difference. Therefore, the output signal of the OR gate 9 becomes low level.

Further, as shown in FIG. 4, when the CPU reads the first check data set so that there is a 1-bit error in the ECC bit, if the ECC circuit 3 is normal, the 1-bit error is corrected. The data stored in the first and second data buffers 5 and 6 match. In this case, as described in the first embodiment, the error / correction result output unit 4 masks without outputting “correction”. Therefore, as in the case shown in FIG. 3, the output signal of the OR gate 9 is at a low level.

As described above, if the output state of each signal is confirmed for each case, it can be confirmed whether or not the function of the ECC circuit 3 is normal.

As described above, according to the second embodiment, the memory 11 includes the check data storage area 12 in which the first and second check data are stored in advance. And reading the second check data, and executing a check sequence for confirming whether the ECC circuit 3 operates as expected, a low level signal is given to one of the input terminals of the AND gate 10 to perform memory diagnosis. The function of the circuit 1 is invalidated. Therefore, it is possible to confirm whether or not the function of the ECC circuit 3 is normal without outputting a reset signal to the outside.

The present disclosure is not limited to the embodiment described above or illustrated in the drawings, and the following modifications or expansions are possible. If there is no problem ignoring the case where a 1-bit error occurs only in the ECC bits, it may be treated as abnormal in (C). Further, the function of the error / correction result output unit 4 may be built in the ECC circuit 3. Further, N may be set to “3” or more. The output signal of the AND gate 10 may not be a reset signal, but an interrupt may be generated in the CPU, for example, and the subsequent processing may be left to the CPU (for example, a reset is issued when the interrupt occurs a plurality of times). .

Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

Claims

An error detection and correction circuit (3) for performing error detection of N bits or more and error correction of (N-1) bits or less for data read after being written to the memory (2, 11);
A first data buffer (5) that stores data read from the memory and error-corrected by the error detection and correction circuit;
A second data buffer (6) directly storing data read from the memory;
A comparator (7) for comparing the value of the data stored in the first data buffer and the value of the data stored in the second data buffer;
An error detection and correction monitoring circuit (8, 9),
In the error detection / correction monitoring circuit, the value of data stored in the first data buffer differs from the value of data stored in the second data buffer by (N−1) bits or less as a result of comparison by the comparator. And when the error detection and correction circuit confirms that the error correction has been performed, the data value stored in the first data buffer is validated,
In the error detection / correction monitoring circuit, i) a value of data stored in the first data buffer and a value of data stored in the second data buffer in the comparison result of the comparator are (N−1) bits. When it is different and the ECC circuit confirms that error correction is not performed, or ii) the value of data stored in the first data buffer and the value of data stored in the second data buffer are (N− 1) If the error detection / correction circuit confirms that error correction has been performed, but the difference is not more than a bit, or iii) the value of data stored in the first data buffer and the second data in the comparison result of the comparator If the value of the data stored in the buffer differs by N bits or more, or iv) confirming that the error detection and correction circuit performs error detection, the first data As invalid data value stored in Tabaffa, outputs an abnormal signal,
The memory diagnostic circuit, wherein N is a natural number of 2 or more.
The error detection / correction circuit includes (N−1) bits in error detection data for performing error detection and correction corresponding to the data, wherein the data stored in the first data buffer has no error of 1 bit or more. 2. The memory diagnosis according to claim 1, wherein when the following error is detected and corrected, the error correction execution on the error detection data is masked to the error detection / correction monitoring circuit. circuit.
First check data set such that a combination of data to be detected and corrected and error detection data for performing error detection and correction on the data is an error of (N-1) bits or less;
A check data storage area (12) in which the second check data set so that the combination results in an error of N bits or more is stored in advance;
When the error detection / correction monitoring circuit (8, 9, 10) is activated, the CPU reads the first check data and the second check data from the check data storage area, and the error detection / correction circuit is as expected. 3. The memory diagnostic circuit according to claim 1, wherein the function of the error detection / correction monitoring circuit is invalidated when executing a check sequence for confirming whether or not to operate normally.