JPH03242745A - Information processor - Google Patents

Abstract

PURPOSE:To improve the use efficiency of a memory by correcting data read out from the memory by corresponding ECC check bits and selecting one of corrected data. CONSTITUTION:Data held in plural memory write registers 1-i are outputted as one data, namely, a write register output 103, and ECC check bits 108 for this data are generated by a check bit generating circuit 3, and the write register output 103 and ECC check bits 108 are stored in a memory 4. Read data 109 read out from the memory 4 is corrected with ECC check bits corresponding to this data by a correcting circuit 5, and one data word of corrected data 110 corrected by the correcting circuit 5 is selected by a data selector 6. Consequently, a bit number ratio of ECC check bits to bits of the data word is reduced through the number of bits of the data word is small. Thus, the use efficiency of the memory 4 is improved.

Description

Detailed Description of the Invention Technical Field The present invention relates to an information processing device, and in particular to a method for storing data with an ECC check bit in a memory. Conventionally, in an information processing device, an ECC check bit is added to one data word. and stored the data word in one word of memory.

That is, E is applied to each of N pieces of data (N is an integer of 2 or more).
CC check bits were added and the data was stored in memory.

In such conventional information processing devices, an ECC check bit is added to one data word and the data word is stored in one word of memory. Therefore, when the number of bits in a data word is small, the data word Since the ratio of the number of ECC check bits to the number of bits becomes large, there is a drawback that memory usage efficiency decreases.

OBJECTS OF THE INVENTION The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above, and an object of the present invention is to provide an information processing device that can improve memory usage efficiency.

Structure of the Invention An information processing apparatus according to the present invention includes: a plurality of holding means each holding a plurality of pieces of data; a generating means generating an ECC check bit by using the data held in each of the holding means as one data; storage means for storing the data held in each of the holding means and the ECC check bit generated by the generation means as one data; and a storage means for correcting the data stored in the storage means with the ECC check bit corresponding to the data. and a selection means for selecting one of the data corrected by the correction means.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, memory write register 1-1 (i=1
．． 2. . )1
03 to the check bit generation circuit 3 and memory 4.

Address decoder 2 decodes address 101 and write enable signal 102, sends set signal 104 to memory write register 1-1, sends memory address 105 and memory write enable signal 106 to memory 4, and sends selection control signal 107 to data selection. output to the respective devices 6.

Check bit generation circuit 3 is memory write register 1-
The write register output 103 from i generates an ECC check bit, and the FCC check bit 10g
is output to memory 4.

That is, the check bit generation circuit 3 generates one ECC check bit for N pieces of data.

Memory 4 is memory address 1 from address decoder 2
05 and memory write enable signal 10G, write register output 1 from memory write register 1-1
03 and an ECC check bit 10g from the check bit generation circuit 3, and outputs read data 109 to the correction circuit 5.

The correction circuit 5 reads the read data 10 read from the memory 4.
9 is corrected, and the corrected data 110 is sent to the data selector 6.
Output to.

The data selector 6 selects one data word from the correction block 110 from the correction circuit 5 in response to the selection control signal 107 from the address decoder 2, and outputs the data word as read data 111.

When writing to the memory 4, the address 101 and write enable signal 102 are decoded by the address decoder 2, and a set signal 10 is sent to the memory write register 1-i.
4 is generated.

In the memory write register 1-i, write data 100 is set in the bits that meet the set condition by the set signal 104 from the address decoder 2.

Write data 10 to all memory write registers 1-1
When set to 0, that is, when N data words are set in the memory write register 1-1, the address decoder 2 specifies the memory address 105 in the memory 4 and sets the memory write enable signal 106 to “1”.
'' to put the memory 4 in a writable state.

At this time, the check bit generation circuit 3 generates an ECC check bit 108 based on the write register output 103.

The write register output 103 from the memory write register 1-i and the ECC check bit 10g from the check bit generation circuit 3 are the memory address of the memory 4 that has become writable by the memory write enable signal 1013 from the address decoder 2. The data is written to the address specified by 195.

When reading from the memory 4, the address i01 is decoded by the address decoder 2, and a memory address 105 to the memory 4 and a selection control signal 877 to the data selector 6 are generated.

The read data 109 read from the memory 4 according to the memory address 105 from the address decoder 2 is error-corrected by the correction circuit 5 and sent to the data selector 6 as corrected data 110.

The data selector 6 receives the correction data +10 from the correction circuit 5 by the selection control signal 107 from the address decoder 2.
One data word is selected and read data 111
is output as

FIGS. 2 and 3 are diagrams for explaining the operation of an embodiment of the present invention. In these figures, the case is shown in which three data words are written into the memory 4.

That is, the memory 4 has three data words D0 to D2.
．． D3-D5. ECCCC check bits ECEC2 and EC3 are added to each of D6 to D8 and stored in association with each other (see FIG. 2).

For example, when reading the data word D5 from the memory 4, the address 5' is input to the address decoder 2 as the address 101, so the address decoder 2 calculates the following equation using 5° of the address 101. and generates a memory address 105 and a selection control signal 107.

X-INT (Y/3) ・・・・・・(1) Z-Y
, MOD, 3 ......(2) Here, (1)
The formula calculates the value (-X) by dividing the address lot (-Y) by 3 and rounding down the decimal places, and formula (2) calculates the remainder (-X) when the address 101 (-Y) is divided by 3. −Z).

Address decoder 2 is the value (-X) determined by equation (1).
is output as the memory address 105, and the value (-Z) obtained by equation (2) is output as the selection control signal 107.

In this case, address +01 is 5', so Y-5 is (1
) and (2), X-1 and Z-2 are obtained.

Therefore, from address decoder 2, memory address +05
"1° is output as the selection control signal 107,"
2° is output.

Memory address 10 from address decoder 2 to memory 4
When 1° is input as 5, three data words D3 to D5 and ECC check bit EC2 are read from memory 4 and sent to correction circuit 5 as read data 109.

The correction circuit 5 corrects errors in the three data words D3 to D5 using the ECC check bit EC2.
Three correction data AU, AI, A2 are corrected data 110
It is output to the data selector 6 as

Since 2° is manually inputted to the data selector 6 from the address decoder 2 as the selection control signal 107, the correction data A2
That is, the corrected data of data word D5 is selected and output as read data 111 (see FIG. 3).

In this way, the data held in each of the plurality of memory write registers 1-i is treated as one data, that is, the write register output 103, and the ECC check bit +08 for that data is generated by the check bit generation circuit 3, and the write register output +03 is generated. and the FCC check bit 108 are stored in the memory 4, the read data 109 read from the memory 4 is corrected by the correction circuit 5 using the ECC check bit corresponding to this data, and the corrected data corrected by the correction circuit 5 is By selecting one data word out of 110 with the data selector 6, even if the number of bits of the data hood is small, the ratio of the number of ECC check bits to the number of bits of the data word is lower than before. Because it is smaller, memory 4
can improve the usage efficiency.

As described in detail, according to the present invention, a plurality of pieces of data held in each of a plurality of holding means are processed into EC as one data.
A C check bit is generated, the data and the ECC check bit are stored in the memory as one data, and the data read from the memory is corrected with the ECC check bit corresponding to the data. By selecting one piece of data, there is an effect that memory usage efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 2 and 3 are diagrams for explaining the operation of the embodiment of the present invention. Explanation of symbols of main parts 1-1 to 1-N...Memory write register 2.
... Address decoder 3 ... Check bit generation circuit 4 ... - Memory 5 ... Correction circuit 6 ... Data selector

Claims (1)

[Claims] (1) A plurality of holding means each holding a plurality of pieces of data, a generation means generating an ECC check bit by using the data held in each of the holding means as one data, and data held in each of the holding means and storage means for storing the ECC check bits generated by the generation means as one data, correction means for correcting the data stored in the storage means with the ECC check bits corresponding to the data, and the correction means 1. An information processing apparatus comprising: selection means for selecting one data from among the data corrected by.