JP3339803B2 - Error correction code generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction code generation circuit, and more particularly to a Reed Solomon code generation circuit.

In recent years, as the data processing speed of information processing apparatuses has been increased, the amount of data processing has been significantly increased. As described above, as the amount of data to be processed increases, an error in data that increases increases becomes a problem. In order to solve this data error problem, redundant data for error detection / correction is added to the processed data.

In order to reduce the ratio of redundant data for error correction to data,
There is a need for a system having an efficient error correction code. In addition, it is required that these circuit scales have no complexity while preventing enlargement.

[0004]

2. Description of the Related Art Error-correcting code Reed Solomon code (RS)
) Will be described by taking an application to a magnetic tape device as an example. In the conventional magnetic tape device, when data is recorded on a plurality of tracks, an error correction code is added to each track to secure data reliability. The error correction code is data 1
In this method, four bytes are added to four bytes (a single logical method).

As described above, in order to generate an error correction code for a small number of data, 14 bytes are processed at a time as an error correction code generation procedure. Therefore, even when data is recorded on a plurality of tracks, there is no need to prepare a code generation circuit for a plurality of tracks. However, data processing demands of information processing apparatuses in recent years tend to increase year by year, and thus it is necessary to increase the amount of data that can be recorded per unit area of a magnetic tape apparatus.

As a method of increasing the data recording amount per unit area, a method of reducing the number of error correction codes added to data to be recorded and adding an efficient error generation code can be considered. For example, there is a method of adding a small number of error correction codes to a large amount of data. In this system, the ability to perform error correction is reduced instead of reducing the amount of error correction code to be added. For this reason, a plurality of error correction codes are used instead of a single logical error correction code, so that a decrease in error correction capability is prevented.

FIG. 5 shows an example of a conventional error correction code generation circuit. In order to generate an error correction code (RS code), a calculation circuit for executing a generator polynomial is required. The calculation circuit is roughly divided into three parts, namely, an accumulator 5-1, an adder 6, and a holding unit 1. Each time one byte of input data is input, the data held by the holding unit 1 is read,
The data is multiplied by the multiplication unit 5 (meaning of multiplication, the same applies hereinafter), the multiplication result is added to the input data (DATA) by the addition unit 6 (EOR), and the result is stored in the same location of the holding unit 1. Since the holding unit 1 operates with a clock, the above operation is processed with one clock.

Generally, the holding unit 1 has a REG (register)
Has been realized. As the calculation of the error correction code, the data in the holding unit (REG) 1 is read out, integrated, and
A function equivalent to realizing the process of writing data into one cycle of a clock is required.

[0009]

When a plurality of error correction codes are used, it is necessary to generate the error correction codes by parallel processing. Therefore, the number of REGs holding a plurality of error correction codes at once increases, and the circuit scale becomes enormous. As the circuit scale increases, the cost increases, and a problem arises in that the demand for downsizing the device cannot be met.

To solve this problem, a configuration is conceivable in which data is held using a memory instead of the REG, but a new problem arises. That is, REG is used to create an error correction code.
In the conventional example using, it was possible to easily initialize a plurality of REGs by performing a clearing process.
If a memory is used for holding data, it cannot be realized unless all addresses of the memory are written. Further, in the generation circuit using the REG as the error correction code, the data of the REG was read, and the result obtained by operating the data could be written at the next clock. But in memory this READ a
fter WRITE processing connects the output of the memory and the arithmetic circuit,
Moreover, it cannot be realized only by connecting the arithmetic circuit and the input of the memory.

[0011]

Means for Solving the Problems An error correction code generating circuit for generating an error correction code corresponding to the data string, prior to
The error correction code generation circuit includes a holding unit including a memory element.
, An address generator, a multiplier, a register, and an adder
And the holding unit is configured with data of a predetermined number of bytes.
Having a storage area corresponding to each of the plurality of data strings,
The address creation unit is adapted to correspond to each of a plurality of data strings.
(1) setting an address of a storage area;
In the multiplication unit, the data corresponding to the predetermined data sequence is stored.
Data read from the storage area and recorded in the register
The data is subjected to predetermined multiplication processing to become multiplication result data,
Sent from the multiplication unit to the addition unit;
The multiplication result data is input to the addition unit.
Data of the i-th predetermined byte of the predetermined data string
Exclusive OR operation is performed to become operation result data,
(3) the operation result data is
In the storage area of the holding unit corresponding to the predetermined data string,
Stored based on the address set in the address creation section
The i-th predetermined number of each of the plurality of data strings
Byte data is processed by (1), (2), (3)
After that, the data of the (i + 1) th predetermined byte of each data string is
The data sequentially performs the processing of (1), (2), and (3),
After completing the processing of the last byte of data,
Based on the operation result data for each stored data string
An error correction code generation circuit for generating an error correction code for each data string .

The memory element has a write port and a read port, and is configured to read and write different addresses in the same cycle.
FIG. 1 shows a configuration diagram of an embodiment of the present invention. By configuring the holding unit 1 of FIG. 1 with a memory element instead of a register, it is possible to reduce the circuit scale when the number of bytes to be stored increases. In order to configure the memory device, a portion for controlling the address of the memory device and a portion for controlling reading and writing are provided. In addition, read the data of the memory element (READ),
The process of integrating and writing to the holding unit is defined as one of clocks (CLOCK).
Error correction code (E
A function to initialize the holding unit before creating CC) is provided.

[0013]

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 denotes a holding unit of the error correction code generation circuit, which is realized by a dual port RAM. 2 and 3
Is an address creation unit for creating a signal for controlling the address of the memory. Reference numeral 4 denotes a write control unit for controlling writing of A PORT. Reference numeral 5 denotes an integration circuit for performing an α integration operation, which is realized by a gate such as AND or OR. 6 has the same E as that of the conventional error correcting code generator shown in FIG.
This is an OR (addition) unit.

Reference numeral 7 denotes a portion provided to solve the following problem which occurs when the holding section 1 is realized by a memory.
That is, the problem is that the holding unit 1 needs to initialize the held data before creating the code, but if the holding unit is realized by REG in the conventional generation circuit, the clear terminal is operated. By doing so, it was possible to initialize all REG parts at once. In the case of a memory, it is necessary to write data to each address to initialize the memory. Instead of this operation, this is realized by having a configuration in which the output can be set to "00" hex by REG7 when data that has not been initialized is read from BPORT.

There is another REG7 function. If a memory is connected to an input of the same memory as it is without holding output data of the memory itself in a portion other than the memory, data currently output cannot be written to the memory. For this purpose, a register having a function of retaining data is provided. This REG7 is
It is not necessary to use REG as long as it has a function of retaining data.

In this embodiment, the generator polynomial G (X) = (X +
α ²⁵⁴ ) (X + α ⁰ ) (X + α) (X + α ² ), code length n = 1
36, based on minimum distance dmin = 5 (check word = 4) (ANSI 128-TRACK, PARALLEL SERPENITINE X3
B5 / 96-164). The data to be processed is 16 tracks ×
2 = 32 pieces of data are processed in the order of tracks on a byte-by-byte basis. Note that regarding the generator polynomial and X, α, etc.,
For example, application to error correction code (Television Society)
Please refer to.

The creation of the error correction code is performed according to the flowchart shown in FIG. In order to perform the operation of the generator polynomial, first, it is necessary to initialize the circuit before processing the data. Therefore, the holding unit 1 is initialized. First one
When processing the byte, the output of REG7 is "00" hex
Initialize with the clear terminal as follows. Now, REG
7, the output of the integrating circuit 5-1 also becomes zero, and when data is input from the input to the EOR 6, the data input to the holding unit is written as it is.

The data to be processed is a total of 32 data of 2 groups of 16 track data. The first group is called EVEN and the second group is called ODD. Processing is
Start with EVEN track 0, then EVEN track 1,
2, 3, 4,..., 15 are sequentially processed. Following the processing of the EVEN track, the ODD tracks 0, 1, 2, 3, 4,.
・ Process in the order of 15 .

[0019]16When you have finished two groups of tracks,
Process. IeThe first byte of a given track
As processing for the data,(1) Holding part 1This predetermined
Storage area set to store track data
The first byte stored inREAD dataAnd Regis
Data from the register 7 to the integrating circuit 5-1.
(2) Calculate the data with integrating circuit 5-1Data of the operation result
The data is sent to the adder 6.(3)The data of this operation result and
This predetermined value input to the arithmetic unit 6Enter the second byte of the track
Force data andToEOR (addition)And save the resulting data.
Send to the holding unit 1.(Four) The resulting data isHolder 1This
A record set to store data for a given track
In the storage areaWRITEBe done. When this series of processing is completedNext
To process the data of the next track,
Storage area of the holding unit 1 where the first byte data is stored
Change the address to the area. Same as (1), (2), (3), (4)
The same processing is performed. Thus, the first byte of each track
When the processing for the data of
Same as (1), (2), (3), and (4)
The same processing is performed.

The loop of the flowchart of FIG. 2 is repeated until the above processing is completed. At the stage when the processing of 132 bytes of each track is completed, the holding unit 1 corresponds to each track.
The data obtained by reading the data from the stored storage area and calculating the data by the integration circuits 5-2 and 5-3 is the error correction code to be obtained.
(d ₀ , d ₁ , d ₂ , d ₃ ).

The address creation circuit needs to be for writing and for reading. However, the address read by B PORT to process each track and the result of the next operation
It is the same as the address for ITE. That is, the relationship between the WRITE address and the READ address has regularity. Looking at the timing of FIG. 4 at the same point on the time axis, the addresses defined in the address control table of FIG. 3 are WRITE and RE.
One address is different from AD. Taking advantage of this fact, only one ADD GEN.
The circuit of the E address is simplified by creating an address obtained by subtracting 1 from the value of the READ address.

When the holding unit 1 is implemented by a memory, a method for solving the problem that initialization cannot be easily performed is as follows.
Although realized by the clear terminal of EG7, a method of providing a gate that does not transmit the output of REG7 may be used. Further, a gate whose output of the integrating circuit 5-1 becomes zero may be used.
Alternatively, a switching circuit may be provided such that the input is directly connected to the input of the memory 1, and the first byte of each track may be written to the holding unit 1. A method not particularly specified may be a method in which the first byte of the first track is written to the holding unit 1.

In this embodiment, the address created by ADD GEN.2 is connected to the READ address (B PORT), and the subtracter 3 is provided for the WRITE address.
Connect the address created in step 2 to the WRITE address, and
For the address (B PORT), an adder may be provided so long as the relationship between the addresses can be maintained.

In the above embodiment, the generator polynomial G (X) = (X + α ²⁵⁴ ) (X + α ⁰ ) (X + α) (X + α
² ) is described, but other generator polynomials of the RS code can be implemented by having the same configuration.

[0025]

As described above, according to the present invention, the circuit scale can be reduced by using the memory as the holding unit in the error correction code generation circuit, and the memory can be used at the same time. Also solve the problem that occurs and change the holding part to RE
The function equivalent to that realized by G is realized by adding a small number of circuits, which contributes to the prevention of an increase in the circuit size of the error correction circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart of error code generation according to the present invention;

FIG. 3 is an address control of the holding unit 1 of the present invention.

FIG. 4 is a timing chart.

FIG. 5 shows a conventional error correction code generation circuit.

[Explanation of symbols]

 1 is a holding unit, 2 is an address creating unit (ADDGEN.), 3 is an address creating unit (subtractor), 4 is a write control unit (WR / RD CTL), and 5-1, 5-2, and 5-3 are integration. Circuit (multiplication circuit), 6 is an adder (EOR), 7 is a register (REG).

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazu Kawasaki 35, Saho, Kato-gun, Hyogo (No address) Inside Fujitsu Peripheral Machinery Co., Ltd. (56) References JP 3-63093 (JP, B2) 63-46854 (JP, B1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 13/00 G06F 11/10 330 H04L 1/00

Claims (4)

(57) [Claims] 1. An error correction code generation circuit for generating an error correction code corresponding to a data string, wherein the error correction code generation circuit includes a memory element.
Section, address creation section, multiplication section, register, and addition
And a holding unit , wherein the holding unit includes a plurality of
A storage area corresponding to each of the data strings, wherein the address creation unit is configured to correspond to each of the plurality of data strings;
It is for setting the address of the storage area, (1) in the multiplier unit, corresponding to the predetermined data sequence
Read from the storage area and recorded in the register.
The multiplied data is multiplied by the specified multiplication process.
Become data, is sent to the addition unit from the multiplication unit, (2) in the adder portion, wherein the multiplied data is the
The i-th predetermined buffer of the predetermined data string input to the adder
Exclusive OR operation is performed on the data of the
And (3) the operation result data corresponds to the predetermined data string.
The address creation unit sets the storage area of the holding unit
And the i-th predetermined byte of each data string of the plurality of data strings.
Data (1), (2), and (3)
Later, the data of the (i + 1) th predetermined byte of each data string
Performs the processing of (1), (2), and (3) sequentially, and finally
After completing the processing of byte data, store it in the holding unit
Based on the operation result data for each data string
An error correction code generation circuit for generating an error correction code for each data string . 2. The memory device according to claim 1, wherein said memory device is a dual port memory, and said first port of said dual port memory is written.
Used for burning, the by using the second port of the dual port memory to read, error correction code generating circuit according to claim 1, characterized in that writing and reading of different addresses in the same cycle. In the error correction code generating circuit 3. The method of claim 2, further provided with address shift section, a second port Karaa of the address formation unit dual port memory
An address to be accessed , wherein the address shift unit sets a value shifted from the address to be accessed from the second port by a fixed value as the address of the first port. An error correction code generation circuit characterized by the following. 4. The error correction code generation circuit according to claim 1, wherein input data is sequentially stored in a storage area of a corresponding address of said memory element in units of bytes, and said data is stored in said storage area until a next cycle. The data stored in the address storage area is multiplied by the multiplying unit at a constant rate, and the result of the multiplication and the data input in the next cycle are subjected to an exclusive OR operation by the adding unit to obtain the exclusive An error correction code generation circuit for storing logical OR data as new data in a storage area of the address.