JPS6398747A - Test system for microprogram - Google Patents

Abstract

PURPOSE:To evaluate all steps of a microprogram by knowing the using state of each step based on the correcting situation of the 1-bit error of each word of the microprogram of a saving area of a memory medium and a control memory part. CONSTITUTION:An overlay module of a microprogram prepared in a saving area of a main memory is inputted to an ECC control circuit 3 and an ECC pattern serving as a 1-bit error is added to each word. Then this ECC pattern is written into a control memory part 1. When this writing action is through, a microprogram in the part 1 is set to a register 2 and the part 3 detects the 1-bit error to correct it automatically. Then the microprogram is carried out based on the corrected data. When an overlay occurs, the overlay module in the part 1 is swept away to the saving area of the main memory and held there. Then the state of the ECC pattern of each word is detected for microprograms of the part 1 and the main memory part. Thus the executing state of a microprogram is grasped.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram test method, and more particularly, to a microprogram test method in which a microprogram having an overlay structure is transferred to a control storage unit, and microprograms in an information processing device controlled by the microprogram after the transfer are performed. This relates to a test method for determining the usage status of a program.

1 In a microprogram-controlled information processing device, if the capacity of the microprogram is so large that the control storage section that stores the microprogram cannot store the microprogram at once, the control storage section and the microprogram are divided. A so-called overlay structure is adopted to efficiently use the control storage section.

In order to confirm the functions of the micro 70 grams of such information processing equipment, the validity of the microprogram is checked using various test programs, and the validity of the operating status of the microprogram is verified using the trace function of the microprogram. things are done. However, it is difficult, almost impossible, to ensure that all steps and combinations of a large microprogram, such as the one with overlay vA3a, have been tested. Therefore, there is a drawback that unevaluated microprogram steps remain.

OBJECTS OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the conventional methods, and its purpose is to provide a microprogram testing method that can evaluate all steps of a microprogram having an overlay structure. There is a particular thing.

According to the present invention, a microprogram having an overlay structure stored in a predetermined storage medium is transferred to a control storage section, and a microprogram testing method is provided in an information processing apparatus controlled by the transferred microprogram. In the test mode, when transferring the microprogram from the storage medium to the control storage section, an error correction code pattern that causes a 1-bit error is added to each word of the microprogram, and the control When executing the microprogram, the microprogram is executed while correcting a one-bit error for each word of the microprogram and rewriting to the control memory, and in response to the occurrence of an overlay, the target of the control memory is The overlay module to be transferred is moved to the evacuation area of the storage medium, the overlay module to be transferred to the storage medium is transferred to the area of the control storage unit where the ejected overlay module was stored, and the overlay module is moved to the evacuation area and A microprogram test method is obtained, characterized in that the usage status of each step of the microprogram is known from the status of correction of 1-bit errors in each word of the microprogram in the control storage section.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which (A) is a block diagram of a control storage section and an ECC (error correction code) control section, and (B) is a block diagram of a section that controls the control storage section. It is a block diagram. In the figure, a control storage section 1 stores microprograms, and the microprograms stored in a main storage section (not shown) are transferred and written via a data line 11. This write data is written into the control storage section 1 via the register 2 that stores the microprogram being executed and the sweep data line 12.

Data read from the control storage unit 1 is temporarily stored in the register 2 via the data line 13 and input to the ECC control mt unit 3. This ECCfljltiO section 3 is a circuit of a well-known configuration having a function of checking the output of the register 2, automatically correcting a 1-bit error, and detecting a 2-bit error. Furthermore, this ECC control unit 3 controls the EC that causes a 1-bit error in response to a 1-bit error instruction 16 from the outside.
It has a function of generating a C pattern and adding it to each word of the corresponding microprogram. If there is no 1-bit error indication 16, a correct ECC pattern is generated.

The output of the ECC control section 3 is stored again in the register 2 via the correction data line 14, and the microprogram in which the 1-bit error has been corrected is rewritten into the control storage section 2 via the return data line 12. It has become.

The overlay control section 4 controls the overlay operation, and the sweeping control section 5 controls the overlay operation in the control storage section 1 in response to the occurrence of overlay timing only when the pit in the mode pit section 6 indicates the test mode. This is a control unit that sweeps out the module to a save area of the main storage section (not shown) via the data line 12 without discarding the module. The mode pit section 6 instructs the overlay control section 4 through an instruction signal line 15 as to which mode is the test mode or the normal mode.
and instructions to the sweep-out control section 5.

In such a configuration, when the information processing apparatus is initialized, some of the microprogram overlay modules prepared in the save area on the main memory are transferred to the write data line 11. The data is inputted to the FCC control section 3 via the register 2, and in the FCC control section 3, an ECC pattern that causes a 1-bit error is added to each word of the corresponding microprogram. The microprogram to which this ECC pattern has been added is temporarily stored in the register 2 via the data line 14 and then written to the specified address section in the control storage section 1 via the sweep data line 12. When the writing is completed, the microprogram at a predetermined address in the control storage section 1 is set into the register 2 via the read data line 13. The information processing device executes various operations according to the contents of this register 2,
The next microprogram is read into register 2, its contents are updated, and subsequent operations are continued.

At this time, since there is a 1-bit error in the contents of register 2, ECCIIJtE section 3 detects this and automatically corrects it, stores this corrected correct data in register 2 via correction data line 14, and stores this corrected data in register 2 via correction data line 14. Executed according to correct data. At the same time, the corrected data is rewritten into the control storage section 1 via the sweep data line 12.

If the next microprogram is not prepared in the control storage unit 1, that is, if an overlay occurs, the overlay operation is performed under the control of the overlay control unit 4. That is, the target overlay module is read from the save area of the main memory section and written into the control memory section 1, but this write operation is performed in the same procedure as the microprogram initial write described above. That is, in the FCC control section 3, an ECC pattern resulting in a 1-bit error is added to each word and written into the control storage section 1. At this time, if mode bit 6 indicates the normal mode, the designated module in control storage unit 1 (the area in the control storage unit where the overlay module read from the main storage unit is written) is stored. ) which designates a module is also taken out and discarded. However, when mode bit 6 indicates test mode,
Although the designated module in the control storage section 1 is flushed out, it is not discarded, but is written and saved as is in the save area in the main storage section via the swept data line 12. Thereafter, the target overlay module will be written into the area in the control storage unit 1 where the swept designated module was stored.

In other words, the difference in operation between normal mode and test mode is
Either the overlay module that is the specified module in the control storage section can be swept out and discarded as is, or it can be written and saved in the evacuation area of the main storage section.

Therefore, in the test mode, the overlay module stored in the f4Q tel storage section is not thrown away as it is in response to the occurrence of an overlay, but is swept out and held in the save area of the main storage section. Therefore,
It becomes possible to detect the status of the ECC pattern of each word of the microprogram left in the save area of the control storage unit and main memory unit, and therefore, if this ECC pattern remains in a pattern state that causes a 1-bit error, , the corresponding microprogram word is not being executed, and conversely, if the ECC pattern is in an error-corrected state, the corresponding microprogram word is being executed, and the microprogram is not executed. This makes it easier to understand the status.

In the above, a microprogram having an overlay structure is stored in the main memory in advance and the execution of the microprogram is controlled while being transferred from the main memory to the control memory. The same application is possible even if the information is stored in a storage medium other than the storage unit.

As described above in JJ and 1, according to the present invention, when a microprogram having an overlay target structure is transferred from a storage medium such as a main memory to a control memory, one bit is transmitted for each word of the microprogram. ECC patterns that result in errors are added to each microprogram before being transferred, and microprograms in the control storage unit that are subject to overlay and should be flushed out are stored in a save area in the storage medium without being discarded at the time of extraction. By leaving this evacuation area and i! 1
By detecting and examining the ECC patterns of the microprograms remaining in each control storage section, it is possible to easily grasp the usage status of the microprograms. Furthermore, since it is not necessary to add an ECC pattern to a microprogram that is previously stored in a storage medium, there is also the effect that the preparation of the microprogram becomes easier.

[Brief explanation of the drawing]

FIGS. 1A and 1B are block diagrams of embodiments of the present invention. Explanation of symbols of main parts 1... Control storage unit 3... Register 4... Overlay υ control unit 5... Sweeping control unit

Claims (1)

[Claims] A microprogram test method in an information processing apparatus in which a microprogram having an overlay structure stored in a predetermined storage medium is transferred to a control storage unit and controlled by the microprogram after the transfer, wherein in a test mode, the above-mentioned When transferring the microprogram from the storage medium to the control storage section, an error correction code pattern that causes a 1-bit error is added to each word of the microprogram and written into the control storage section, and the microprogram is transferred to the control storage section. During execution, each word of the microprogram is corrected for one-bit errors and rewritten to the control storage section, and in response to the occurrence of an overlay, the overlay module targeted by the control storage section is written to the storage medium. The overlay module to be transferred on the storage medium is transferred to the area of the control storage unit where the removed overlay module was stored, and each of the microprograms in the evacuation area and the control storage unit is A microprogram test method characterized in that the usage status of each step of a microprogram is known from the correction status of a 1-bit error in a word.