JPS58159158A - Detecting system for fault of address bus - Google Patents

Abstract

PURPOSE:To improve the efficiency of maintenance and to shorten the time of a fault or to improve the reliability for a detecting system for fault on an address bus, by always separating the fault on the address bus from those due to other factors. CONSTITUTION:When a central processing part 1 gives a device access to an input/output control part 3, an address is designated on an address bus 5 and a desired data is sent onto a data bus 6. For an address bus fault detecting circuit 4, an address bus parity error detecting circuit 4A gives a parity check to the address information on all address spaces with the bus 5. When a parity error is detected, the data on buses 5 and 6 of that time are held at an address bus information latching circuit 4B and a data bus information latching circuit 4C respectively. At the same time, a flag 4D is set up to display the generation of a parity error.

Description

[Detailed description of the invention] This is related to the output method.

The conventional address bus failure detection method of this stock is, for example,
Parity errors were detected only in the input circuit of the accessed device based on address information on the address bus.

Therefore, if address information is changed due to a failure on the address bus and a non-existent device is accessed according to the incorrect address information, no response will be received from any device to the central processing unit of that device.

In this case, there is a problem in that the central processing unit cannot determine whether the non-response is due to a failure in the accessed device or a failure on the address bus.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address bus failure detection method that eliminates the above-mentioned drawbacks of the prior art and can always distinguish between failures on the address bus and failures caused by other failure factors such as failures in accessed devices. It is in.

The present invention is characterized by an address bus failure detection method for a device that is equipped with a central processing section, a memory section, an input/output control section to which addresses are assigned, and necessary devices between them, and these are connected and configured by a common bus. An address bus failure detection circuit capable of detecting a parity error on the address bus related to the common bus for all address spaces is connected to the address bus, and when a parity error occurs on the address bus, the address bus information By retaining data bus information and setting a flag to indicate this, the central processing unit can respond to a non-response when accessing a device according to the contents of both bus information and flags. The present invention is an address bus fault detection method that can detect and isolate address bus faults or faults caused by other factors.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a system configuration diagram of an embodiment of the address bus fault detection method according to the present invention, and FIG. 2 is an address configuration diagram thereof.

Here, 1 is a central processing unit, 2 is a memory unit, 3 is an input/output control unit, 4 is an address bus fault detection circuit, 4A
is its address bus parity error detection circuit; 4B is an address bus information latch circuit for holding address bus information at the time of the same failure; 4C is a data bus information latch circuit for holding data bus information at the time of the same failure; 4D is a flag for indicating the occurrence of the same address bus integrity error, 5 is an address bus related to the common bus, and 6 is the same data bus.

For example, when the central processing unit 1 makes device access to the input/output control unit 3, it first specifies the address on the address bus 5 and sends desired data onto the data bus 6.

In this case, as shown in FIG. 2, the address of the input/output control unit 3 is (AO) to (4F)H in hexadecimal.

(FO)H to (FF), for example, the address (AO)H (location marked A in Figure 2)
Assume that even though the address (EO) H (marked by B in FIG. 2) is specified, an incorrect specification (or a pit change due to a bus failure) occurs for some reason.

This erroneous address (EO) H is not assigned to any device, so in the end, for the central processing unit 1,
There will be no response.

In addition to the above, the entire address space includes addresses (00)H to (7F)u, (σO)H to (
E! Fh is assigned address (80)
H~(9F)H, (BO)H~(BF)n, (DO)
H to (EF)H are free addresses or capacity addresses that are not assigned to any device.

On the other hand, in the address bus fault detection circuit 4, the address bus parity error detection circuit 4A performs a parity check on the address information (data) of all address spaces for the address bus 5, and when a parity error is detected, 5. Data on data bus 6 (
Address bus information and data bus information) are held in the address bus information latch circuit 4B and data bus information latch circuit 4C, respectively, and a flag 4D is set to indicate that a parity error has occurred.

However, in the case of no response to the device access described above, the central bribe calling unit 1 first checks the flag 4D of the address bus failure detection circuit 4, and sets the flag 4D.
If flag 4D is set, there is a fault related to address bus 5, or if flag 4D is not set,
It is possible to identify (separate) that it is an access device failure, and for both, the address bus M report and data bus information can be obtained from the address bus information latch circuit 4B and the data bus information latch circuit 4C, This is also useful information for failure recovery measures such as analysis and isolation of failure causes.

In the above embodiment, the address bus fault detection circuit 4 is described as being an independent circuit, but it is not necessarily limited to that.
This does not preclude installation as part of other devices. In other words, a device equipped with this can not only perform the original accessed operation, but also perform the same operation related to address bus failure detection as described above using the attached address bus failure detection circuit 4. it is obvious.

As described in detail above, according to the present invention, it is possible to always distinguish between failures on the address bus and failures caused by other failure factors. ) can have remarkable effects on improving the efficiency of maintenance work, shortening failure times, and improving reliability.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of an embodiment of the address bus fault detection method according to the present invention, and FIG. 2 is an address configuration diagram thereof. 1... Central AL1 section, 2... Memory value, 3... Input/output control unit, 4... Address bus failure detection circuit, 4A
...Address bus parity error detection circuit, 4B...
Address bus information latch circuit, 4C...data bus information latch circuit, 4D...flag, 5...address bus, 6...data bus. Agent: Patent attorney Kosaku Fukuda (and one other person)

Claims (1)

[Claims] 1. In the address bus fault detection method for a device that is equipped with a central processing unit, a memory unit, a people distribution control unit to which addresses are assigned, and other necessary devices, and these are connected and configured by a common bus, the entire address space of the device is An address bus failure detection circuit capable of detecting a parity error on the address bus related to the common bus is connected to the address bus, and when a parity error occurs on the address bus, the address bus information/data bus information is By retaining this information and setting a flag to indicate this, the central processing unit can respond to a non-response during device access by detecting an address bus failure or an address bus failure or An address bus failure detection method that is characterized in that failures caused by other factors can be detected and isolated intelligently.