JPS63261436A - Parity error recovery system - Google Patents

Abstract

PURPOSE:To prevent normal data from being misdecided as abnormal data by effectively utilizing cells in a parity memory, and at the time of detecting a parity error due to the failure of a cell, retrying operation without immediately deciding data abnormality. CONSTITUTION:A PC/PG circuit 1 sends parity bits corresponding to data obtained from a terminal A to a writing means 6. The means 6 stores the bits in all the cells of the parity memory 3. Every time that a parity checker in the circuit 1 sends a parity error, a reading means 7 selects one of bits read out from different cells in the memory 3 and sends the selected bit to the circuit 1. After selecting bits read out from all the cells of the memory 3, the means 7 sends abnormality report to a processor 5. When no abnormality is detected in thee error of the circuit 1 and the means 7 generates the abnormality report, the processor 5 decides data abnormality, so that the generation of misdecision can be prevented.

Description

[Detailed Description of the Invention] [Summary] When performing a parity check, when a corresponding cell of a memory element that stores a parity bit added to data becomes a failure, the memory element is checked so that the data does not become an error. Parity bits are stored in N cells, and each time a parity error is detected, a parity bit read from a different cell of the memory device is selected and parity check is performed eight times to ensure that no errors are detected. When this occurs, it is determined that the data is abnormal.

[Industrial application field]

In the present invention, when a parity bit is added to data to check for errors that occur in the data, the present invention prevents the data from becoming an error when a cell of a memory device that stores the parity bit added to the data becomes a failure. Regarding parity error recovery methods.

In information processing devices and the like, for example, when writing to/reading from memory, a parity check is performed to ensure the reliability of data.

Therefore, when writing data to memory, a parity generator generates a parity bit, and the generated parity bit is stored in the parity memory. When reading data from the memory, the parity bit is stored in the parity memory. The stored parity bit is sent to the parity checker and added to the data to perform a parity check.

Therefore, if a failure occurs in the corresponding cell of the parity memory that stores parity bits, the parity bits will differ from those generated by the parity generator, and a parity error will occur, causing normal data to be incorrectly determined to be abnormal. Therefore, when a fault occurs in a parity memory cell, it is necessary to recover from this parity error.

[Conventional technology]

FIG. 3 is a block diagram illustrating the conventional technology.

When data is written to a memory (not shown), terminal A
For example, 8-bit data is input to a PC/PC (parity check/parity generator) circuit 1.

At this time, since "O" is sent from the processor 5 to the AND circuit 2, the AND circuit 2 continues to send "0". The parity generator of the PC/PG circuit 1 creates a parity bit corresponding to the input data, sends the created parity bit to the parity memory 3, and the parity memory 3 stores this parity bit in the corresponding cell.

When data is read from the memory, "l" is sent from the processor 5 to the AND circuit 2, the parity bit read from the parity memory 3 is input to the AND circuit 2, and if the parity bit is "1", the AND circuit 2 is sent. “1” from circuit 2
” is sent out, and if the parity bit is “O”, “0” is sent out from the AND circuit 2.

The parity check of the PC/PG circuit 1 is performed by adding a parity bit sent from the AND circuit 2 to the data read from the memory input from the terminal A, and if there is an error, a "dead" is sent to the flip-flop 4. Send and set.

Therefore, flip-flop 4 reports a parity error to processor 5, and processor 5 determines that this data read from memory is abnormal.

[Problem that the invention seeks to solve]

When the parity memory 3 in FIG. 3 uses the same storage element as the memory that records data, if the data is, for example, 8 bits, then if 1 bit is used for the parity bit,
The remaining 7 bits of cells are unused. Moreover, when one cell of the memory element that stores the parity bit fails, as described above (normal data becomes a parity error,
There is a problem in that data is incorrectly determined to be abnormal.

[Means for solving problems]

When the storage element of the parity memory 3 has cells that store N bits, the present invention stores the parity bits in unused cells as well, and sequentially reads out the N bits of parity bits from different cells to create a PC/PC circuit. The processor 5 determines that there is an abnormality in the data only when the data is sent to the first parity check and all errors occur.

FIG. 1 is a block diagram of the principle of the present invention.

The parity generator of the P C/P C circuit 1 is
As explained in the figure, a parity bit corresponding to the data input from terminal A is generated and sent to the writing means 6. The writing means 6 stores this parity bit in the parity memory 3.
Send and write to all cells at once.

The reading means 7 reads the parity memory 3 every time the parity check of the PC/PG circuit 1 sends out a parity error.
The parity bits read from different cells are sequentially 1
Bit by bit is selected and extracted and sent to the PC/PG circuit l. When the parity bits read from all the cells of the parity memory 3 have been selected, an abnormality report is sent to the processor 5.

The processor 5 does not recognize the parity error sent by the PC/PC circuit 1 as a data abnormality, but determines that the data is abnormal when the reading means 7 issues an abnormality 1 notification.

[Effect]

With the above configuration, the writing means 6 stores parity bits in all the cells of the parity memory 3, and the reading means 7 sequentially selects the parity bits from each cell of the parity memory 3, and reads the P.C. /PC circuit 1, the utilization efficiency of the parity memory 3 increases, and even if one cell of the parity memory 3 becomes defective, if the other cells are normal, normal data is sent to the parity memory 3. It is possible to prevent an error from being determined as abnormal.

〔Example〕

FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention.

The same reference numerals as in FIG. 3 indicate the same functions. For example, 8-bit data written to memory from terminal A is P'C/
Input to PC circuit 1. When writing data, "O" is sent from the processor 5 to the AND circuit 2, so the AN
The D circuit 2 continues to send out "0".

The circuit generator of the PC/PC circuit l creates a parity bit corresponding to the input data and sends it to the driver 10.
Send to. The driver 10 has the same number of write circuits as the cells included in the parity memory 3, and
The parity bit is sent to all cells in the cell.

Therefore, the parity memory 3 can store parity bits in all cells.

When reading data, from the processor 5 to the AND circuit 2
If "1" is sent to A and the parity memory 3 has cells from ■ to ■, the multiplexer 1) first selects the parity bit read from the cell
Enters the ND circuit 2, and if the parity bit is “L”, the AN
"1'" is sent from D circuit 2, and the parity bit is "
O'', the AND circuit 2 outputs “0”.

The parity check of the PC/PG circuit 1 is performed by adding a parity bit sent from the AND circuit 2 to the data read from the memory input from the terminal A, and if there is an error, a "dead" is sent to the flip-flop 9. Send and set.

Therefore, flip-flop 9 sends "1" to processor 5 and up counter 12. The "1" sent by the flip-flop 9 is the highest level interrupt signal to the processor 5, and when the processor 5 uses this interrupt to set the internal try flag, it resets the flip-flop 9 via the register 8 and releases the interrupt. At the same time, the process moves to recovery processing, sends "l" again to the AND circuit 2, reads out the same data from the memory again, and inputs it to the terminal A.

Up counter 12 outputs “
1'' counts up - times and multiplexer 1
), selects the parity bit read from the cell 2 of the parity memory 3, and sends the extracted parity bit to the PC/PG circuit 1 via the AND circuit 2.

When the parity check of the PC/PG circuit 1 detects a parity error again and sets the flip-flop 9, the up counter 12 counts up again - times, switches the multiplexer 1), and stores the parity memory 3. The parity bit read from the cell is selected, and the extracted parity bit is sent to the PC/PC circuit 1 via the AND circuit 2.

Similarly to the above, the processor 51 resets the flip-flop 9 via the register 8 and inputs the same data to the terminal A. Repeating this operation, even when the multiplexer 1) selects the parity bit read from cell 2 of the parity memory, when a parity error is sent from the PC/PC circuit 1, the up counter 12 A carry signal is sent to the processor 5.

When processor 5 receives the carry signal from up counter 12, it determines that the data is abnormal.

If only the cell ■ of parity memory 3 becomes defective,
Since the parity bit read from cell (2) is normal, no parity error is sent from the PC/PG circuit 1. Therefore, the up counter 12 stops after counting and amplifying once. Therefore, from now on, the multiplexer 1) will continue to select the parity bit of the cell (■) of the parity memory 3, so by selecting the parity bit of the defective cell (■), the PC/PCI
The parity check will not repeat parity error detection.

〔Effect of the invention〕

As explained above, the present invention makes effective use of parity memory cells, and when a parity error is detected due to a failure in a parity memory cell, the data is not immediately determined to be abnormal, but is processed up to N times. You can recover by trying.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a block diagram illustrating a conventional technique. In the figure, 1 is a P C/P 0 circuit, 2 is an AND circuit, 3 is a parity memory, 4.9 is a flip-flop, 5 is a processor, 6 is a writing means, 7 is a reading means, 8 is a register, and 10 is a Driver: 1) is a multiplexer, 12 is an up counter. Ku

Claims (1)

[Claims] Parity memory (3
), the parity generator (1) sends and writes the generated parity bit, and the parity bit written by the parity generator (1) is read from the parity memory (3). In a circuit equipped with a parity checker (1) that performs a parity check by adding this parity bit to the input data when a parity error is detected, and reports an error to the processor (5) when a parity error is detected, The parity generator (
a writing means (6) for sending and writing N bits of parity bits generated by the parity checker (1) at a time; A reading means (7) sequentially extracts the parity bits read out from the parity memory (3) by selecting different cells from each other, and reports an abnormality to the processor (5) when the selection is made N times. ), and causes the parity checker (1) to perform a parity check based on the parity bit extracted by the reading means (7), and when a parity error is sent N times, it is determined that the data is abnormal. A parity error recovery method characterized by determining.