JPH08153013A - Error detection circuit - Google Patents

Abstract

PURPOSE: To shorten the response time while the reliability of data is improved by selecting the number of retry times sufficient for majority decision and executing retry for the number of times when a parity error is detected so as to execute majority decision. CONSTITUTION: A memory 1 reads data by the control of a control circuit 2. Read data is parity-checked in an error detection circuit 3. A parity error detection signal and read data are inputted to a retry control circuit. The retry control circuit 4 executes a retry processing n-times, more than three times, which is previously decided, when the parity error is detected in read data. Respective pieces of data and the error detection signals are inputted to a data holding circuit 5 through the retry control circuit 4 so as to hold them. When n-times of retry is finished, a majority decision circuit 6 decides the majority of data which is not error-detected among data held by the data holding circuit 5, and result data is outputted to CPU 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection circuit, and more particularly to a parity error detection circuit for detecting a data parity error.

[0002]

2. Description of the Related Art Generally, there is a parity error detection method for performing a parity check as a simple method for detecting the presence or absence of an error in read data from a memory or the like. By this parity check, when a parity error is detected, an error flag is immediately generated and the host device C
Report to PU etc.

Further, there is a system in which, when an error is detected, instead of immediately reporting the error to the host device, a retry process is performed and read data is received again from the same memory address, as disclosed in Japanese Unexamined Patent Publication No. 2-208874. It is disclosed.

[0004]

Parity check is 1
In the method of performing only once, when the error is not due to a fixed fault but due to an external factor such as noise, the error can be resolved by retrying, but the system goes down with only one error detection. There is a risk that it will occur.

In the method of performing the retry process, the number of retries is often one, and thus the above-mentioned problem cannot be completely solved. Further, if the retry control is performed by software processing, there is a disadvantage that the response time from error detection until the retry result is output becomes long.

Further, in the parity check method, even-numbered bit errors cannot be detected in the case of odd-numbered parity. Therefore, if a parity error is detected and data of the same address is read again by retry processing, the reliability will be insufficient. .

It is an object of the present invention to provide an error detection circuit which uses a retry process to improve the reliability of data and shorten the response time.

[0008]

An error detecting circuit according to the present invention comprises a parity error detecting means for detecting a parity error of input data, and a supply of the input data in response to the detection of the parity error by the parity error detecting means. It includes an instruction means for instructing the supply of the input data a predetermined number of times of three times or more predetermined to the original, and a majority decision means for making a majority decision of the input data a predetermined number of times. The feature is that it is derived as output data.

[0009]

When a parity error is detected in the input data from the memory or the like, the input data is retried three times or more and the majority of the acquired data is taken three or more times. The output data resulting from this majority decision is derived as correct data.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Data is read from the memory 1 under the control of the memory control circuit 2, and the read data is subjected to a parity check in the error detection circuit 3. The parity error detection signal from the error detection circuit 3 and the read data are input to the retry control circuit 4.

The retry control circuit 4 performs a retry process of n times or more when a parity error is detected in the read data. The retry process instruction is issued to the memory control circuit 2. Will be issued. Therefore, the memory control circuit 2 performs memory access by the same read address n times.

Each data and the error detection signal by the retry of n times are input to the data holding circuit 5 via the retry control circuit 4 and held. When the retry of n times is completed, the majority circuit 6 takes the majority of only the data held in the data holding circuit 5 and no error is detected, and outputs the majority result data to the CPU 7. If the majority decision circuit 6 cannot take a majority decision,
An error is reported to the CPU 7.

FIG. 2 is an operation flowchart of the retry control. In the memory read, if no parity error is detected, the read data is regarded as correct and retry processing is not performed, and the next memory read is performed. When a parity error is detected in this memory read (step 21), retry processing of memory read of the same address n times is performed (step 22).

The majority of the read data is taken n times (step 23), but the data in which the parity error is detected is not allowed to participate in the majority vote. For example, FIG. 3 shows the data of the retry process of n = 5 times and the result of the parity check. If even parity is used, the data of the second time is a parity error and therefore the majority decision cannot be entered. The 4th data from the 1st and 3rd to 5th will participate in the majority vote, resulting in "0000".
Since the data of "0" is three times and the data of "0110" is once, "0000" is derived as correct data.

There are cases in which a large number of parity errors occur and a majority decision cannot be taken. At this time, an error report is made to the host device 7 such as a CPU and the processing ends (steps 24, 25).

[0017]

According to the present invention, the number of retries is selected to be a sufficient number (three or more) so that a majority decision can be taken, and when a parity error is detected, a retry is performed for that number of times to take a majority decision. Therefore, there is an effect that the reliability of the data is remarkably improved and the response speed can be increased because all the hardware can be configured.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an operation flow chart of the embodiment of the present invention.

FIG. 3 is a diagram showing an example of data, parity, and a majority decision result by a retry process.

[Explanation of symbols]

 1 memory 2 memory control circuit 3 error detection circuit 4 retry control circuit 5 data holding circuit 6 majority circuit 7 CPU

Claims (3)

[Claims] 1. A parity error detecting means for detecting a parity error of input data, and a predetermined number of times of three or more times predetermined for a source of the input data in response to detection of a parity error by the parity error detecting means. It is characterized in that it includes an instruction means for instructing the supply of the input data a predetermined number of times and a majority decision means for making a majority decision of the input data a predetermined number of times, and the result of majority decision of the majority decision means is derived as output data. Error detection circuit. 2. The error detection circuit according to claim 1, wherein the majority decision means reports an error to a host device when a majority decision cannot be taken. 3. The input data is read data from a memory, and the instructing means is configured to instruct the memory to read data at the same address a predetermined number of times. 2. The error detection circuit described in 2.