JP2979584B2 - Reading method of semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a reading method of a semiconductor memory device.

[Prior Art] A conventional semiconductor memory device having a plurality of cascade-connected sense amplifiers as a data read circuit section has a configuration as shown in FIG. Then, the output buffer 641 is driven by the sense amplifier 621 of the next stage or later receiving the sense output, so that the read operation is performed at high speed. Further, in a semiconductor memory device having a configuration in which the number of words is large, as shown in FIG. 7, the configuration in which the words are divided reduces the number of memory cells assigned to each of the sense amplifiers 711, 712,. Like that.

[Problems to be Solved by the Invention] In these conventional semiconductor memory devices, the first-stage sense amplifier must continuously perform a read operation to the last-stage sense amplifier within the same cycle. That is, the output of the first stage sense amplifier reaches the last stage sense amplifier,
Until output from the output buffer, these sense amplifiers must maintain a read operation. For this reason, in the case of a semiconductor memory device having a particularly large scale and a large number of words and using multiple stages of sense amplifiers, it takes much time for the input of the first stage sense amplifier to reach the last stage. For this reason, the standby time for reading the next signal becomes longer, which is a problem when the operating speed (data rate) of the semiconductor memory device is increased.

[Means for Solving the Problems] The gist of the present invention is to provide a first sense amplifier group in which each read data signal connected to each memory cell is input and one selected sense amplifier operates, and A switch circuit for selectively connecting and outputting each output of the first sense amplifier group and selectively passing an output of one first sense amplifier selected from the first sense amplifier group; A second sense amplifier to which an output of the first sense amplifier that has passed through a switch circuit is input, wherein the read operation is performed by operating the selected first sense amplifier. A first step of opening a switch circuit and transmitting an output of the first sense amplifier to an input section of the second sense amplifier, and stopping the operation of the first sense amplifier; A second circuit for closing the switch circuit and operating the second sense amplifier;
Are sequentially repeated in the opposite phase to each other, so that reading is performed by a pipeline operation.

[Operation] By interposing a switch circuit at the cascade connection point of the cascade-connected sense amplifiers, the operation timing of the sense amplifier at the preceding stage and the sense amplifier at the subsequent stage of the switch circuit can be reduced by half.
The read operation can be performed in a pipeline operation shifted by one cycle or one cycle. Therefore, the read operation from the first-stage sense amplifier to the last-stage sense amplifier can be performed in a time-divided manner, and the read operation can be performed at a higher data rate than the conventional semiconductor memory device.

Example Next, the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of the first embodiment of the present invention. Read data signals DR1, ▲ ▼, DR from memory cells
A switch circuit is provided between the first stage sense amplifiers 211, 212, 213,... For sensing 2, ▲ ▼, DR3, ▲ ▼,. 201 comprises P-type MOS transistors 251, 252 and N-type MOS transistors 253, 254. First stage sense amplifiers 211, 212, 213, ...
When one of them is selected by a control signal CA11, CA12, CA13,... To perform a read operation, the control signal CL, ▲
The switch circuit 201 is rendered conductive by (inverted signal of CL), and the output of the first stage sense amplifier is transmitted to the input section of the next stage sense amplifier 221. At the next timing, the operation of the first stage sense amplifier is stopped, and
The switch circuit 201 is cut off by L and ▲ ▼, the sense amplifier 221 is operated by the control signal CA21, the signal is sent to the output buffer 241, and the output signal DO is output. At this time, the input of the sense amplifier 221 is held by the gate capacitance, the diffusion capacitance, and the wiring capacitance of the MOS transistor. Absent. At the next timing, the first stage sense amplifier is operated again to turn on the switch circuit 201 to read the next data, and the same operation as described above is repeated to read data.

In this embodiment, if the reading by the first-stage sense amplifier is completed and the data is passed to the input side of the next-stage sense amplifier, an address change or the like for the next reading can be performed. Therefore, the operation time (data rate) can be improved by shortening the cycle time in the read operation.

FIG. 3 is a block diagram showing a second embodiment of the present invention. A switch circuit 301 having a configuration in which capacitive elements 361 and 362 are newly added to the switch circuit 201 of the embodiment shown in FIG. 2 is used. The other configuration is the same as that of the first embodiment, and the same reference numerals are given and the duplicate description will be omitted. By adding the capacitors 361 and 362 in this manner, the switching circuit 301
When the MOS transistors 251-254 are turned off,
Signal holding at the input section of the sense amplifier 221 is facilitated,
Reading can be performed without causing a malfunction even at a low speed operation.
The other operations are the same as in the first embodiment.

FIG. 4 is a block diagram showing a third embodiment of the present invention. This is a case where word division is performed by using three stages of the sense amplifiers of the present embodiment, and the sense amplifiers 411, 412,.
A switch circuit 404 between the circuit and the sense amplifier 421 in the middle stage
, And a switch circuit 402 is provided between the sense amplifiers 421, 422,. Each switch circuit 401, 402 is a P-type MOS transistor 451,
452, 455, 456, and N-type MOS transistors 453, 454, 457, 458. The switch circuits 401 and 402 operate in opposite phases according to the control signal CL, ▲ ▼. In such a configuration, the first stage sense amplifier and the last stage sense amplifier operate in the same phase, and the middle stage sense amplifier operates in the opposite phase. Also,
The switch circuit 401 is turned on while the first-stage sense amplifier is operating, and the switch circuit 402 is turned on while the intermediate-stage sense amplifier is operating. As a result, when the output signal DO is output, the next read data reaches the input of the sense amplifier 421 in the intermediate stage, and when the output signal DO is read, the address and the like for the next read are further changed. It can be carried out. That is, since reading can be performed one after another by the pipeline operation, even when word division is performed in multiple stages, high-speed operation can be performed with a reduced data rate.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention. This embodiment is an embodiment in which the sense amplifiers are operated in the same phase in all stages. That is, in the present embodiment, the first-stage sense amplifiers 511, 512, 513,... And the next-stage sense amplifier 521 are operated in the same phase. A switch circuit 521 is provided between the first-stage sense amplifier and the next-stage sense amplifier.The switch circuit 501 is turned off when the sense amplifier is operating, and turned on when the sense amplifier is stopped. It is controlled by the control signal CL, ▲ ▼ to be as follows. According to such a configuration, when the first-stage sense amplifier operates, charges are accumulated in the capacitance elements 561 and 562 of the switch circuit 501. Then, the operation of the first stage sense amplifier is stopped, and the P-type MOS transistors 551, 552,
N-type MOS transistors 553 and 554 turn on and switch circuit 50
When 1 becomes conductive, the charges of the capacitors 561 and 562 move to the capacitors 563 and 564, respectively, and the signal is held at the input of the sense amplifier 521 even when the switch circuit 501 is cut off, and the output to the output buffer 541 is output. It is performed without trouble. Here, if the capacitance of the capacitors 561 and 562 is about twice the capacitance of the capacitors 563 and 564, the input potential of the sense amplifier 521 can be easily inverted. Further, the N-type MOS transistors 555 and 556 are added to prevent the potential difference from being easily inverted when the input potential difference of the sense amplifier 521 becomes larger than necessary and the next read data is inverted.

Thus, while the sense amplifier is not operating, the switch circuit 501 can transfer data and set the address of data to be read next, so that even when all stages of sense amplifiers operate in the same phase, pipeline operation can be performed.
A high data rate can be realized.

[Effects of the Invention] As described above, according to the present invention, in a semiconductor memory device having a plurality of cascade-connected sense amplifiers as a data read circuit unit, one or more cascade-connections of the cascade-connected sense amplifiers are provided. Since the switch circuits are connected to each other in a dependent manner, the read operation can be performed by a pipeline operation by shifting the operation timing of the sense amplifier in the preceding stage and the sense amplifier in the subsequent stage by one half cycle or one cycle. Thus, the read operation from the first-stage sense amplifier to the last-stage sense amplifier can be performed in a time-divided manner, and the read operation can be performed at a higher data rate than the conventional semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example for explaining the concept of the present invention, FIG. 2 is a block diagram of a first embodiment of the present invention, FIG. 3 is a block diagram of a second embodiment of the present invention, FIG. Is a block diagram of a third embodiment of the present invention, FIG. 5 is a block diagram of a fourth embodiment of the present invention, and FIGS. 6 and 7 are block diagrams of conventional examples. 101,201,301,401,402,501 ... Switch circuit, 111,121,211,212,213,221,411,412,421,422,431,511,51
2,513,521,611,621,711,712,721,722,731 ... sense amplifier, 141,241,441,541,641,741 ... output buffer, 251,252,451,452,455,456,551,552 ... P-type MOS transistor, 253,254,453,454,457,458,553,554,555,556 ... N-type MOS
Transistor, 361,362,561,562,563,564 ... Capacitance element, DR, ▲ ▼, DR1, ▲ ▼, DR2, ▲ ▼, DR3, ▲
▼: Read data signal, DO: Output signal, CA11, CA12, CA13, CA21, CA22, CA31, CL, ▲ ▼: Control signal.

Claims (2)

(57) [Claims] 1. A first sense amplifier group in which each read data signal connected to each memory cell is input and one selected sense amplifier operates, and each output of the first sense amplifier group is A switch circuit that is commonly connected and input and selectively passes an output of one first sense amplifier selected from the first sense amplifier group; and a first sense circuit that passes through the switch circuit. A second sense amplifier to which an output of the amplifier is input, wherein the read operation is performed by operating the selected first sense amplifier, opening the switch circuit, and performing the first sense operation. A first step of transmitting an output of the amplifier to an input section of the second sense amplifier, stopping the operation of the first sense amplifier, closing the switch circuit, and closing the second sensor; The method of reading a semiconductor memory device is characterized in that the read by sequentially repeating the second step of operating the amplifier in opposite phase to each other to perform a pipeline operation. 2. A first sense amplifier group in which each read data signal connected to each memory cell is input and one selected sense amplifier operates, and each output of the first sense amplifier group is provided. A switch circuit that is commonly connected and input and selectively passes an output of one first sense amplifier selected from the first sense amplifier group; and a first sense circuit that passes through the switch circuit. A second sense amplifier to which an output of the amplifier is input, a first capacitive element having one end connected between the common connection point of the first sense amplifier group and the switch circuit and the other end grounded;
A method for reading a semiconductor memory device, comprising: a second capacitive element having one end connected between the switch circuit and the second sense amplifier and the other end grounded, wherein the selected first A first step of operating a sense amplifier to accumulate the charge from the output of the first sense amplifier in the first capacitive element; stopping the operation of the first sense amplifier and opening the switch circuit; And a second step of moving the charge accumulated in the first capacitance element to the second capacitance element is sequentially repeated. In the first step, the second sense amplifier is operated and the switch circuit is operated. Closing, and simultaneously performing a third step of amplifying the electric charge accumulated in the second capacitive element by the second sense amplifier, thereby allowing the first sense amplifier and the second sense amplifier to perform the same operation. The method of reading a semiconductor memory device in is operated, characterized in that to perform the read pipeline operation.