JP4102381B2 - Analog FIFO memory - Google Patents

Description

  The present invention relates to an analog FIFO memory, and particularly relates to a technique for improving the accuracy of an analog FIFO memory by eliminating an error in an analog signal between writing and reading.

  As is well known, conventional television signal processing techniques are implemented using analog circuits. Among TV signal processing technologies, the most developed technology in recent years is the Y / C separation technology. Y / C separation is a technique for separating a luminance signal (Y signal) and a color difference signal (C signal) from a color television signal. Y / C separation has been conventionally performed using an analog bandpass filter or an analog band elimination filter, but in recent years, Y / C separation has been realized that skillfully utilizes the properties of color television signals. .

  The Y / C separation will be described with reference to FIG. FIG. 26A shows the frequency spectrum of the NTSC color television signal. As shown in FIG. 26A, the frequency spectrum of the luminance signal in the NTSC color television signal is modulated and distributed from the DC to around 4.2 MHz at the frequency of the horizontal synchronization signal of the NTSC color television signal. On the other hand, the frequency spectrum of the color difference signal is similarly modulated and distributed with the frequency of the horizontal synchronizing signal of the NTSC color television signal so as to be nested with respect to the luminance signal centered on 3.57954 Mz. Therefore, in order to separate the luminance signal (Y signal) and the color difference signal (C signal), a filter having a transfer function as shown in FIG.

  For this purpose, as shown in FIG. 27 (a), the NTSC color television signal (NTSC Composite) is delayed by one cycle of the horizontal synchronization signal of the NTSC color television signal and added to the original NTSC color television signal. Subtract. That is, in order to realize the Y / C separation as described above, an analog memory circuit is required in order to delay by one cycle of the horizontal synchronizing signal of the NTSC color television signal.

  Conventionally, a CCD circuit has been used as such an analog memory circuit. However, since the CCD circuit is manufactured using a process technology different from the silicon process for manufacturing bipolar transistors and CMOS transistors, there is a problem that it cannot be formed on the same silicon wafer as bipolar transistors and CMOS transistors. For this reason, in the conventional TV signal LSI, as shown in FIG. 27 (b), an NTSC color television signal processing circuit has to be realized with an external analog memory composed of a CCD circuit.

  Therefore, an attempt has been made to realize a one-chip TV signal LSI as shown in FIG. 27C by configuring an analog FIFO memory with a bipolar transistor or a CMOS transistor circuit.

  FIG. 28A is a diagram showing a basic configuration of a conventional analog FIFO memory (Ken A. Nishimura et al. “A Monolithic Analog Video Comb Filter in 1.2-μm CMOS”, IEEE Journal of Solid-State Circuite, Vol. .28, No. 12, December 1993, pp1331-1339). In FIG. 28A, reference numeral 1 denotes a memory bus circuit including memory buses 13A and 13B to which a memory cell 10 is connected, and 2 denotes a switched capacitor sample hold (SCSH) that writes an input signal to the memory cell 10 of the memory bus circuit 1. ) A write circuit having a circuit 20 and an operational amplifier 25, and 3 is a read circuit for reading an output signal from the memory cell 10 of the memory bus circuit 1. The memory bus circuit 1 includes input means 15 for controlling signal input from the write circuit 2 and output means 16 for controlling signal output to the read circuit 3. Here, it is assumed that the conventional analog FIFO memory shown in FIG. 28A is driven by high-active two-phase clock signals φ1 and φ2 as shown in FIG.

  When the clock signal φ1 is active, the SCSH circuit 20 turns on the switches 22a and 22c and samples and holds the input analog signal in the capacitive element 21. Further, since the switches 16A and 16B of the output means 16 are turned on and the memory buses 13A and 13B are both at the analog ground potential, the charge stored in the capacitor element 11 of the memory cell 10 is the capacitance of the read circuit 3 according to the charge conservation law. Transferred to the element 31.

  Next, when the clock signal φ2 becomes active, the SCSH circuit 20 turns on the switches 22b and 22d, and both ends of the capacitive element 21 become the analog ground potential. Therefore, the charge of the capacitive element 21 follows the charge conservation law. It is transferred to the capacitive element 11. Of course, at this time, the switches 15A and 15B of the input means 15 are turned on. At this time, the analog switch 32 of the readout circuit 3 is also turned on, and the charge accumulated in the capacitor 31 is discharged. When the clock signal φ1 becomes active again, the charge stored in the capacitive element 11 of the memory cell 10 is transferred to the capacitive element 31 according to the law of conservation of charge as in the previous case.

By such an operation, the analog signal sampled by the SCSH circuit 20 is once stored in the memory cell 10 and transferred to the capacitive element 31 of the reading circuit 3. Here, assuming that the capacitance value of the capacitive element 21 is C1 and the input signal voltage is Vin, the charge amount Qin stored in the capacitive element 21 is as follows.
Qin = Vin · C1 (1)
Since the charge accumulated in the capacitive element 21 is transferred as it is to the capacitive element 11 of the memory cell 10, the same charge amount Qin is stored. Furthermore, since the electric charge stored in the capacitive element 11 is transferred to the readout circuit 3, the voltage Vout generated at both ends of the capacitive element 31 at this time is as follows when the capacitance value of the capacitive element 31 is C3.
Vout = Vin · C1 / C3 (2)

  The operation as described above is ideal, and if such an operation can be realized, there is no problem with the conventional circuit. However, in practice, in the conventional analog FIFO memory, the written analog signal is not always accurate at the time of reading. Therefore, there is a problem that an error occurs in an analog signal between writing and reading.

  There are two main causes for such an analog signal error.

  The first is charge accumulation due to parasitic capacitance such as inter-wiring capacitance existing between memory buses.

  In the conventional analog FIFO memory shown in FIG. 28, when the inter-wiring capacitance 61 exists, when the clock signal φ1 is active (that is, during the write operation), the capacitance element 21 of the write circuit 2 to the memory cell 10 A part of the charge to be transferred to the capacitor element 11 is accumulated in the inter-wiring capacitor 61. The charge stored in the interwiring capacitor 61 is transferred to the read circuit 3 as it is when the clock signal φ2 becomes active (that is, during the read operation). In other words, the charge accumulated in the inter-wiring capacitor 61 during the write operation is output from the memory bus circuit 1 during the subsequent read operation.

  On the other hand, an analog FIFO memory performs a read-modify-write operation, that is, an operation in which an analog signal is read from a memory cell and then a new analog signal is written to the memory cell. It is changed after being written. In the conventional analog FIFO memory as shown in FIG. 28, the address of the memory cell changes between the time when the clock signal φ1 becomes active and the time when the clock signal φ2 becomes active.

  Accordingly, the fact that the charge accumulated in the inter-wiring capacitor 61 during the write operation is output during the subsequent read operation means that the analog signal that has been written in one memory cell in the past and should be read out by this read operation. In addition, it means that a part of the analog signal to be written to another memory cell is added by the immediately preceding write operation and output from the memory bus circuit 2. That is, the analog signal read from the analog FIFO memory includes an error corresponding to the electric charge accumulated in the inter-wiring capacitor 61 by the write operation immediately before the read operation.

For example, assuming that the charge stored in one memory cell in the past is Qm, when the charge Qm is normally read from the one memory cell, the output voltage Vout should be as follows.
Vout = Qm / C3 (3)
However, when the inter-wiring capacitance Cp exists, if the analog signal Vs is written in another memory cell (capacitance value is C2) by the writing operation immediately before the reading operation, the following charge Qp is generated in the wiring. It will be stored in the interspace Cp.
Qp = C1 · Vs · Cp / (Cp + C2) (4)
Therefore, in the read operation of the one memory cell, the voltage generated by the charge Qp is added to the voltage value shown in the equation (3) and output, so the output voltage Vout is as follows.
Vout = Qm / C3
+ (C1 / C3) · Vin · Cp / (Cp + C2) (5)

  Another cause is the memory bus potential difference between the read operation and the write operation, and the memory bus potential variation for each read operation.

In the conventional analog FIFO memory shown in FIG. 28, when the clock signal φ2 becomes active and the transfer of charges from the capacitive element 21 of the write circuit 2 to the capacitive element 11 of the memory cell 10 is completed (that is, when the write operation is completed). ), The potential of the memory bus 13A becomes the analog ground potential, while the potential Vb of the memory bus 13B becomes as follows.
Vb = Vang + Vin (6)
Here, Vang is an analog ground potential, and Vin is a written analog signal potential. That is, the potential of the memory bus 13B at the start of the read operation changes under the influence of the analog signal written immediately before.

  On the other hand, when an analog signal is read from the memory cell 10, the potentials of the memory buses 13A and 13B are both analog ground potentials. Therefore, at the start of the write operation, the potentials of the memory buses 13A and 13B are both analog ground potentials.

  That is, the potential of the memory bus 13B is different between the read operation and the write operation. In addition, since the potential of the memory bus 13B in the read operation is affected by the analog signal written by the immediately preceding write operation, it varies for each read operation.

  When an analog FIFO memory is manufactured by a silicon process, the memory bus usually has many parasitic capacitances that are difficult to estimate in advance. For this reason, when reading an analog signal from the memory cell, the charge stored in the parasitic capacitance of the memory bus may also be read together. As described above, the potential of the memory bus is read out. And the write operation differ, and each read operation varies, so that an error caused by the parasitic capacitance of the memory bus occurs in the analog signal.

  As described above, in the conventional analog FIFO memory, the written analog signal cannot always be accurately reproduced at the time of reading due to the influence of the parasitic capacitance such as the capacitance between the wirings of the memory bus, that is, the analog signal at the time of writing and at the time of reading. There was a problem that errors would occur.

  In view of the above problems, an object of the present invention is to reduce an error of an analog signal between writing and reading as an analog FIFO memory so that the written analog signal can be read with high accuracy.

The solution provided by the invention of claim 1 is connected to each memory cell as a plurality of memory cells for storing analog signals as analog FIFO memories for delaying the input analog signals by a predetermined time and outputting them in the input order. A memory bus circuit having a memory bus for transferring an analog signal, the memory cell having a capacitor element for storing the analog signal in the form of electric charge, and a switch for switching control of a connection state between the capacitor element and the memory bus; And the switch is turned on during a read operation and a write operation when the memory cell is selected as a target for reading and writing an analog signal, and the memory bus circuit includes the memory bus connected to the dummy memory cell including a capacitor having the same capacitance value as the capacitor element of the memory cell It is one that is equipped to.

  According to the first aspect of the present invention, since the capacity of the memory cell at the time of analog signal writing is apparently increased by the dummy memory cell having the capacitive element connected to the memory bus, the influence of the charge transfer error caused by the parasitic capacity of the memory bus. Can be made relatively small. Therefore, the influence of the parasitic capacitance of the memory bus on the input / output characteristics of the analog FIFO memory can be reduced.

  According to a second aspect of the present invention, in the analog FIFO memory of the first aspect, the dummy memory cell is provided so as to sandwich the plurality of memory cells at both ends of the memory bus.

  According to the invention of claim 2, since the change of the impedance of the memory bus due to the layout position of the memory cell to be read and written is reduced, the settling characteristic of the memory bus circuit can be stabilized, and the analog FIFO memory The input / output characteristics can be improved.

  According to the present invention, by providing a dummy memory cell, it is possible to reduce the influence of the parasitic capacitance of the memory cell on the input / output characteristics of the analog FIFO memory.

(First embodiment)
1A and 1B are diagrams showing an analog FIFO memory according to a first embodiment of the present invention. FIG. 1A is a diagram showing a schematic configuration, and FIG. 1B is a diagram showing a schematic operation.

  As shown in FIG. 1A, the analog FIFO memory according to the present embodiment includes a memory bus circuit 1 having a memory bus to which a memory cell for storing an analog signal is connected, and an analog signal via the memory bus. Is constituted by a writing circuit 2 for writing data and a reading circuit 3 for reading an analog signal from the memory cell via a memory bus.

  A feature of the analog FIFO memory according to the present embodiment is that a reset operation for removing charges accumulated in the parasitic capacitance of the memory bus is performed before the read operation. That is, as shown in FIG. 1B, the operation of the analog FIFO memory according to the present embodiment is basically divided into three, reset, read, and write. First, the memory bus is reset by a reset operation, and then an analog signal is read from a memory cell (address m) connected to the reset memory bus by a read operation. At this time, the amount of electric charge accumulated in the memory cell from which the analog signal has been read becomes 0, so that the input signal is written to this memory cell by the next write operation.

  In the conventional analog FIFO memory, there is a problem that an analog signal read from the analog FIFO memory is affected by an analog signal written in the analog FIFO memory immediately before due to the presence of the parasitic capacitance of the memory bus. Therefore, in order to eliminate the influence of the analog signal written immediately before, the operation of resetting the memory bus is performed before the read operation of the analog signal.

  FIG. 2 is a circuit diagram showing an example of the configuration of the memory bus circuit 1. In FIG. 2, 10 is a memory cell for storing an analog signal, 13 is a memory bus comprising first and second bus lines 13A and 13B, and 15 is an input means for controlling the connection state between the write circuit 2 and the memory bus 13. , 16 are output means for controlling the connection state between the read circuit 3 and the memory bus 13. The memory cell 10 includes a capacitor element 11 and a switch 12 which are connected in series between the first and second bus wirings 13A and 13B and store analog signals in the form of electric charges. The switch 12 is a memory cell switch. On / off switching is controlled by the switch control means 12c that operates according to the drive signal S1 and the memory cell selection signal SL. The input means 15 includes switches 15A and 15B. The switches 15A and 15B are ON / OFF controlled by a switch control means 15c that operates according to the input switch drive signal S2 and the memory cell selection signal SL. The output means 16 includes switches 16A and 16B. The switches 16A and 16B are ON / OFF controlled by a switch control means 16c that operates according to the output switch drive signal S3 and the memory cell selection signal SL.

  The memory bus reset is an operation of setting the potentials of the first and second bus wirings 13A and 13B to the same potential or a constant potential difference when the memory bus circuit 1 as shown in FIG. 2 is taken as an example. As a result, the charge accumulated in the parasitic capacitance of the memory bus 13 becomes 0 or constant, and the analog signal read operation is not affected by the analog signal written immediately before.

  FIG. 3A is a diagram illustrating an example of the configuration of the write circuit 2, and FIG. 3B is a diagram illustrating an example of the configuration of the read circuit 3. As shown in FIG. 3A, the write circuit 2 includes a switched capacitor sample and hold circuit (SCSH circuit) 20 and an operational amplifier 25. The SCSH circuit 20 is a capacitive element that temporarily stores an input signal in the form of charges. 21 and switches 22a, 22b, 22c and 22d. The switches 22a and 22c are ON / OFF controlled by the first write switch drive signal S4, while the switches 22b and 22d are ON / OFF controlled by the second write switch drive signal S5. As shown in FIG. 3B, the readout circuit 3 includes a capacitive element 31 that temporarily stores an output signal in the form of electric charge, a switch 32, and an operational amplifier 33. The switch 32 is controlled to be turned on and off by the read switch drive signal S6.

  The reset operation, read operation, and write operation of the analog FIFO memory according to this embodiment will be described with reference to FIGS.

  4 to 6 are diagrams showing the configuration of the analog FIFO memory according to the present embodiment when the circuit configurations of FIGS. 2 and 3 are used in the schematic configuration of FIG. 4 shows a state during the reset operation, FIG. 5 shows a state during the read operation, and FIG. 6 shows a state during the write operation. Reference numeral 61 denotes a parasitic capacitance of the memory bus 13, which is a capacitance between wirings between the first and second bus wirings 13A and 13B. 4 to 6, only one memory cell 10 is shown to simplify the description, and control means and signals related to the control of each switch are omitted.

  In the reset operation according to the present embodiment, the first bus line 13A and the second bus line 13B are set to a predetermined potential (for example, an analog ground potential), and the capacitive element connected in parallel with the operational amplifier 33 in the read circuit 3 The charge amount of 31 is set to zero. As a result of such a reset operation, the first and second bus wirings 13A and 13B have the same potential, and therefore the amount of charge accumulated in the inter-wire capacitance 61 of the first and second bus wirings 13A and 13B becomes zero. Become. Further, since the potentials of the first and second bus lines 13A and 13B are equal at the start of the read operation and the start of the write operation, the influence of the interwiring capacitance 61 between the first and second bus lines 13A and 13B. The charge can be read from the memory cell 10 without receiving the charge.

  The read circuit 3 is used for the reset operation according to the present embodiment. That is, as shown in FIG. 4, in the reset operation, the switches 15A and 15B of the input means 15 of the memory bus circuit 1 are turned off and the switches 16A and 16B of the output means 16 are turned on and connected to the memory bus 13. The switches 12 of all the memory cells 10 that have been turned off are turned off. Further, the switch 32 of the readout circuit 3 is turned on. At this time, the reverse-phase and positive-phase input terminals 33a and 33b of the operational amplifier 33 of the readout circuit 3 are at the same potential, and thereby output to the reverse-phase and positive-phase input terminals 33a and 33b of the operational amplifier 33 of the readout circuit 3. The first and second bus lines 13A and 13B of the memory bus circuit 1 connected through the means 16 are at the same potential. For this reason, the charge stored in the inter-wiring capacitor 61 is discharged, and the charge amount of the inter-wiring capacitor 61 becomes zero. In this way, the reset operation in the analog FIFO memory according to this embodiment is completed.

  Next, a read operation is performed following the reset operation. As shown in FIG. 5, in the read operation, the switch 32 of the read circuit 3 is turned off to release the reset state of the operational amplifier 33. Thereafter, the switch 12 of the memory cell 10 is turned on, and the charge accumulated in the capacitor element 11 of the memory cell 10 is transferred to the capacitor element 31 of the read circuit 3. When the charge transfer is completed, the first and second bus lines 13A and 13B of the memory bus circuit 1 are set to the same potential again. In this way, the read operation is completed.

  In the reset operation and the read operation, in the SCSH circuit 20 of the write circuit 2, the switches 22a and 22c are turned on and the switches 22b and 22d are turned off. As a result, the input analog signal is accumulated in the capacitive element 21 of the SCSH circuit 20 in the form of electric charges.

  Next, a write operation is performed following the read operation. As shown in FIG. 6, in the write operation, the switches 15A and 15B of the input unit 15 of the memory bus circuit 1 are turned on, and the switches 16A and 16B of the output unit 16 are turned off. On the other hand, in the SCSH circuit 20 of the writing circuit 2, the switches 22b and 22d are turned on and the switches 22a and 22c are turned off. At this time, the charge accumulated in the capacitive element 21 of the SCSH circuit 20 is transferred to the capacitive element 11 of the memory cell 10 by the operational amplifier 25 of the writing circuit 2.

(Modification of the first embodiment)
FIG. 7 is a diagram showing a configuration of a read circuit 3A according to this modification, which is used in place of the read circuit 3 of the normal analog FIFO memory shown in FIG. In the readout circuit 3A according to this modification shown in FIG. 7, instead of the switch 32 in the readout circuit 3 of a normal analog FIFO memory, the negative phase input terminal 33a and the output terminal 33c of the operational amplifier 33 are connected to an analog ground power source. There are provided first and second switches 32A and 32B for switching whether or not. Both the first and second switches 32A and 32B are controlled by a read switch drive signal S6.

  In the readout circuit 3 shown in FIG. 3B, the role of the switch 32 is to short-circuit the negative phase input terminal 33a and the output terminal 33c of the operational amplifier 33, and to set the potential of the negative phase input terminal 33a and the output terminal 33c to the analog ground potential. Thus, the charge amount of the capacitive element 31 is made zero. However, if the reverse-phase input terminal 33a and the output terminal 33c are short-circuited, the readout circuit 3 may become unstable and oscillate.

  In the operational amplifier 33 fed back by the capacitive element 31 as shown in FIG. 3B, when the charge on the reverse phase input terminal 33a side of the capacitive element 31 is fixed, the charge of the capacitive element 31 cannot move. Therefore, the state of the operational amplifier 33 is also stabilized. This indicates that the state of the operational amplifier 33 becomes unconditionally stable. In other words, in a circuit that transfers charge to a capacitor connected in parallel between the negative-phase input terminal 25a and the output terminal 25c of the operational amplifier 25, such as the SCSH circuit 20, the circuit is always stable when the charge transfer is completed. Will not enter the oscillation state.

  That is, there is a possibility that the readout circuit 3 as shown in FIG. 3B becomes unstable, that is, enters an oscillation state, when the switch 32 is turned on.

  Therefore, in the readout circuit 3A according to this modification shown in FIG. 7, when the negative phase input terminal 33a and the output terminal 33c of the operational amplifier 33 are short-circuited, both the negative phase input terminal 33a and the output terminal 33c are directly connected to the analog ground power source. By connecting, the potential is forced to an analog ground potential.

  That is, in the readout circuit 3A shown in FIG. 7, when the negative-phase input terminal 33a and the output terminal 33c of the operational amplifier 33 are short-circuited, the first and second switches 32A and 32B are both turned on and the negative-phase input terminal The circuit is reset by setting the potentials of 33a and 33c to the analog ground potential. By such a system, when the negative phase input terminal 33a and the output terminal 33c of the operational amplifier 33 are short-circuited, the potential is forcibly fixed to the analog ground potential by the analog ground power supply. Therefore, it is possible to realize a stable read circuit 3A without the risk of oscillation in any state.

  Note that the first embodiment of the present invention can be easily applied to an analog FIFO memory including a plurality of memory bus circuits 1 each having a plurality of memory cells 10.

  FIG. 8 is a diagram showing an example of a circuit configuration when an analog FIFO memory is configured as a plurality of memory buses. A configuration in which a plurality of memory bus circuits 1 are configured in parallel between a write circuit 2 and a read circuit 3 is shown. Show. In FIG. 8, connection terminals 4a and 4b to the writing circuit 2 and connection terminals 5a and 5b to the reading circuit 3 are shown, and the writing circuit 2 and the reading circuit 3 are not shown.

  In FIG. 8, reference numeral 41 denotes an address generation circuit that outputs a memory cell selection signal SL. Memory cell selection signal SL is divided into two, row address selection signals SR1 to SR3 and column address selection signals SC1 to SC3. Here, since all the signals are assumed to be low active, the switch control means 15c of the input means 15 is realized by the OR gate 15d, and the switch control means 16c of the output means 16 is realized by the OR gate 16d. That is, in the input means 15, when both the row address selection signals SR1 to SR3 and the input switch drive signal S2 are "L", the switches 15A and 15B are turned on. In the output means 16, the row address selection signals SR1 to SR3 are turned on. And the output switch drive signal S3 are both “L”, the switches 16A and 16B are turned on. In other words, only the memory bus circuit 1 selected by the row address selection signals SR1 to SR3 can turn on the switches 15A and 15B of the input unit 15 and the switches 16A and 16B of the output unit 16.

  Next, a method for driving the switch 12 of the memory cell 10 will be described. The switch 12 of the memory cell 10 includes one of row address selection signals SR1 to SR3, one of column address selection signals SC1 to SC3, and a memory cell switch drive signal S1 generated by the OR gates 12d and 12e. It is driven by an OR signal. Therefore, only the memory cell 10 selected by the row address selection signal and the column address selection signal can transmit the memory cell switch drive signal S1 to the switch 12. For example, in FIG. 8, when the row address selection signal SR2 and the column address selection signal SC2 become “L”, only the memory cell 10x can transmit the memory cell switch drive signal S1 to the switch 12. That is, since the memory bus circuit 1 and the memory cell 10 can be freely selected by the row address selection signal and the column address selection signal, an analog signal can be written to and read from any memory cell 10.

  FIG. 9 is a diagram for explaining a specific addressing method of the analog FIFO memory. FIG. 9 shows an analog FIFO memory having m rows and n columns of memory cells. In FIG. 9, reference numeral 42a denotes an m-ary counter that designates an upper bit of a memory address, and reference numeral 42b denotes an n-ary counter that designates a lower bit of the memory address. The upper counter 42a and the lower counter 42b constitutes an address signal generation circuit. The lower counter 42b performs an increment operation in accordance with an externally applied clock. Reference numeral 43 denotes an overflow signal of the lower counter 42 b, and the upper counter 42 a performs an increment operation in accordance with the overflow signal 43.

  That is, the memory address advances in order (1, 1), (1, 2), (1, 3) by the increment operation of the lower counter 42b, and when it reaches (1, n), the overflow signal 43 is output from the lower counter 42b. Since it is output, the upper counter 42a performs an increment operation, whereby (2, 1) is designated as the memory address. Similarly, after the memory address is designated up to (m, n), the process returns to (1, 1) again. Therefore, the analog signal written in each memory cell is read after (m * n * T), where T is the period of the clock applied to the lower counter 42b.

  The timing of switching the memory cell address in the present embodiment is after writing a signal to the memory cell, as shown in FIG. That is, after the input analog signal is written to the memory cell, the next memory cell is accessed, and the analog signal is read after the reset operation. At this time, the analog signal written before (m * n * T) is stored in this memory cell as described above. Therefore, by the addressing as shown in FIG. 9, it operates as an analog FIFO memory having a delay time (m * n * T).

(Second Embodiment)
FIG. 10 is a diagram showing an outline of the configuration of an analog FIFO memory according to the second embodiment of the present invention. As shown in FIG. 10, the analog FIFO memory according to the second embodiment of the present invention includes first and second memory units 101a and 101b having the same configuration, and the first and second memory units. Reference numerals 101a and 101b respectively denote a memory bus circuit 1 having a memory bus to which a memory cell for storing an analog signal is connected, a write circuit 2 for writing an analog signal to the memory cell via the memory bus, and a memory cell to the memory bus via the memory bus. The readout circuit 3 is configured to read out an analog signal.

  Reference numeral 5 denotes a sample and hold circuit that samples and holds analog signals output from the first and second memory units 101a and 101b. Reference numeral 51 denotes an analog signal output from the first and second memory units 101a and 101b. A capacitive element that accumulates in the form of electric charge, 52a is a switch that controls connection / non-connection between the first memory unit 101a and the capacitive element 51, and 52b is a connection / non-connection between the second memory unit 101b and the capacitive element 51. A switch 53 that controls switching of connections is a buffer amplifier. The switch 52a is controlled by the first sample and hold switch drive signal S7, while the switch 52b is controlled by the second sample and hold switch drive signal S8.

  FIG. 11 is a diagram showing an outline of the operation of the analog FIFO memory according to this embodiment shown in FIG. As shown in FIG. 11, in the analog FIFO memory according to the present embodiment, both the first and second memory units 101a and 101b repeatedly perform a reset operation, a read operation, and a write operation as in the first embodiment. . The first and second memory units 101a and 101b operate in parallel, and in synchronization with the clock signal, one performs a write operation while the other performs a reset operation and a read operation. As a result, input / output of an analog signal is performed every clock cycle.

  As shown in FIGS. 10 and 11, in this embodiment, the analog FIFO memory is divided into two memory units 101a and 101b having the same configuration, and each is operated in parallel. Such a parallel configuration is extremely effective when used for delaying TV signals, for example. This will be described.

  FIG. 29 is a diagram showing an outline of the operation of a conventional analog FIFO memory. As shown in FIG. 29, the conventional analog FIFO memory performs an analog signal read operation and write operation for each clock cycle. That is, the time that can be allocated to the read operation and the write operation is half of the clock cycle. Usually, when the NTSC color signal is delayed using an analog FIFO memory, the clock period is about 70 ns. Therefore, the time allocatable to the read operation or the write operation is about 35 ns. In order to read and write analog signals within this time, a very high speed operation is required for the analog FIFO memory. During this time, it is possible to perform operations other than reading and writing such as a reset operation. Virtually impossible.

  In the analog FIFO memory according to the present embodiment, since the two memory units 101a and 101b are configured in parallel and the read operation and the write operation are executed in parallel, the time required for the read operation and the write operation is twice as long as the conventional one. It is possible to allocate a margin of time during which the reset operation can be executed before the read operation. Therefore, for example, even when used for delaying a TV signal, the reset operation can be executed before the read operation.

  A specific operation of the analog FIFO memory according to the present embodiment will be described in detail with reference to FIGS.

  FIG. 12 is a diagram showing a configuration of the analog FIFO memory according to the present embodiment when the circuit configurations of FIGS. 2 and 3 are used in the schematic configuration of FIG. FIG. 12 also shows control signals for controlling each switch. For simplicity of explanation, only one memory cell 10 is shown in each of the first and second memory portions 101a and 101b.

  As shown in FIG. 12, the control signal M1R1 is given as the first write switch drive signal S4 of the write circuit 2 and the output switch drive signal S3 of the memory cell circuit 1 in the first memory unit 101a, while the second Are supplied as the second write switch drive signal S5 of the write circuit 2 and the input switch drive signal S2 of the memory cell circuit 1. That is, the control signal M1R1 controls the switches 22a and 22c of the write circuit 2 and the switches 16A and 16B of the memory cell circuit 1 in the first memory unit 101a, while the write circuit 2 in the second memory unit 101b. The switches 22b and 22d and the switches 15A and 15B of the memory cell circuit 1 are controlled.

  On the other hand, the control signal M2R1 is provided as the second write switch drive signal S5 of the write circuit 2 and the input switch drive signal S2 of the memory cell circuit 1 in the first memory unit 101a, while in the second memory unit 101b. The first write switch drive signal S4 of the write circuit 2 and the output switch drive signal S3 of the memory cell circuit 1 are provided. That is, the control signal M2R1 controls the switches 22b and 22d of the write circuit 2 and the switches 15A and 15B of the memory cell circuit 1 in the first memory unit 101a, while the write circuit 2 in the second memory unit 101b. The switches 22a and 22c and the switches 16A and 16B of the memory cell circuit 1 are controlled.

  The control signal M1R2 is given as a read switch drive signal S6 of the read circuit 3 of the first memory unit 101a and a second sample hold switch drive signal S8 of the sample hold circuit 5. That is, the switch 32 of the read circuit 3 and the switch 52b of the sample hold circuit 5 of the first memory unit 101a are controlled by the control signal M1R2.

  On the other hand, the control signal M2R2 is given as the read switch drive signal S6 of the read circuit 3 of the second memory unit 101b and the first sample hold switch drive signal S7 of the sample hold circuit 5. That is, the switch 32 of the reading circuit 3 and the switch 52a of the sample hold circuit 5 of the second memory unit 101a are controlled by the control signal M2R2.

  The control signal M1R3 is given as the memory cell switch drive signal S1 of the memory bus circuit 1 of the first memory unit 101a, and is input to the OR gate 12f together with the control signal M2R1. The switch 12 of the memory cell 10 of the first memory unit 101a is controlled by a logical sum signal of the control signals M1R3 and M2R1. On the other hand, the control signal M2R3 is given as the memory cell switch drive signal S1 of the memory bus circuit 1 of the second memory unit 101b, and is input to the OR gate 12f together with the control signal M1R1. The switch 12 of the memory cell 10 of the second memory unit 101b is controlled by a logical sum signal of the control signals M2R3 and M1R1.

  FIG. 13 is a diagram showing a time change of each control signal for controlling the analog FIFO memory shown in FIG. In FIG. 13, all the control signals are low active signals. M1Address is a memory cell address of the first memory unit 101a, and M2Address is a memory cell address of the second memory unit 101b.

  As shown in FIG. 13, the operation of the analog FIFO memory shown in FIG. 12 is divided into four modes MODE1 to MODE4 according to the time change of each control signal. 14 to 17 are diagrams showing states in the respective modes MODE1 to MODE4 of the analog FIFO memory shown in FIG. The operation of each mode of the analog FIFO memory shown in FIG. 12 will be described with reference to FIGS.

(MODE1)
First, in MODE1, the first memory unit 101a performs a reset operation of the memory bus 13 for reading operation and sampling of an input analog signal, while the second memory unit 101b performs a write operation.

  The read circuit 3 is used for the reset operation of the memory bus 13. That is, as shown in FIG. 14, in the first memory unit 101a, the switch 32 of the readout circuit 3 is turned on and the switches 16A and 16B of the output means 16 are turned on. Then, the first bus wiring 13A and the second bus wiring 13B are both at the analog ground potential, and the charge stored in the capacitor 31 is also zero. At this time, the switch 12 of the memory cell 10 is turned off so that the capacitor 11 is not reset. At the same time, the switches 22 a and 22 c of the SCSH circuit 20 are turned on, whereby the input analog signal is sampled by the capacitive element 21.

  On the other hand, in the second memory unit 101b, the switches 22b and 22d of the SCSH circuit 20 are turned on and the switches 15A and 15B of the input means 15 are turned on, so that the charge of the capacitive element 21 is transferred to the memory bus 13 Is transferred to the capacitive element 11 of the memory cell 10 via That is, a write operation is performed. Further, at this time, the switch 52 b of the sample hold circuit 5 is turned on, whereby the output analog signal of the read circuit 3 is sampled by the capacitive element 51 of the sample hold circuit 5.

(MODE2)
Next, in MODE2, the first memory unit 101a performs a read operation. That is, as shown in FIG. 15, in the first memory unit 101a, the switch 32 of the read circuit 3 is turned off and the switch 12 of the memory cell 10 is turned on, whereby the capacitor element 11 of the memory cell 10 is turned on. Is transferred to the capacitive element 31 of the readout circuit 3 via the memory bus 13.

  On the other hand, the second memory unit 101b continues to perform the write operation, but the sample and hold circuit 5 enters the hold state when the switch 52b is turned off.

(MODE3)
In MODE3, contrary to MODE1, the first memory unit 101a performs a write operation, while the second memory 101b performs a reset operation of the memory bus 13 for a read operation and sampling of an input analog signal.

  That is, as shown in FIG. 16, in the first memory unit 101a, the switches 22b and 22d of the SCSH circuit 20 are turned on and the switches 15A and 15B of the input means 15 are turned on. The charge of the element 21 is transferred to the capacitor element 11 of the memory cell 10 via the memory bus 13. Further, at this time, the switch 52 a of the sample hold circuit 5 is turned on, whereby the output analog signal of the read circuit 3 is sampled by the capacitive element 51 of the sample hold circuit 5.

  On the other hand, in the second memory unit 101b, by turning on the switch 32 of the reading circuit 3 and turning on the switches 16A and 16B of the output means 16, the memory bus 13 and the capacitive element of the reading circuit 3 are turned on. 32 is reset. At the same time, the switches 22 a and 22 c of the SCSH circuit 20 are turned on, whereby the input analog signal is sampled by the capacitive element 21 of the write circuit 2.

(MODE4)
Finally, in MODE 4, contrary to MODE 2, the second memory unit 101 b performs a read operation. That is, as shown in FIG. 17, in the second memory portion 101b, the switch 32 of the read circuit 3 is turned off and the switch 12 of the memory cell 10 is turned on, whereby the capacitor 11 of the memory cell 10 is turned on. The accumulated charge is transferred to the capacitive element 31 of the read circuit 3 via the memory bus 13. On the other hand, the first memory unit 101a continues to perform the write operation, but the sample and hold circuit 5 enters the hold state when the switch 52a is turned off.

  By repeating the operations in the respective modes MODE1 to MODE4, the operation of the analog FIFO memory according to the present embodiment as shown in FIG. 11 can be realized.

  It should be noted that control may be performed by each control signal so that one of the first and second memory units 101a and 101b operating in parallel performs a read operation while the other performs a write operation and a reset operation.

  Further, three or more memory units each having the memory bus circuit 1 may be provided and operated in parallel. In this case, for example, when one memory unit performs a write operation, another memory unit may perform a read operation, and another memory unit may perform a reset operation during this time.

(Third embodiment)
FIG. 18 is a diagram showing an outline of the configuration of an analog FIFO memory according to the third embodiment of the present invention. As shown in FIG. 18, the analog FIFO memory according to the third embodiment of the present invention includes a plurality of memory bus circuits 1 each having a memory bus to which memory cells for storing analog signals are connected. Reference numeral 6 denotes a sample-and-hold circuit that samples and holds the analog signal output from the readout circuit 3. Reference numeral 61 denotes a capacitive element that accumulates the analog signal output from the readout circuit 3 in the form of charges. Reference numeral 62 denotes the capacitance of the readout circuit 3 and the capacitor. A switch 63 controls switching between connection / disconnection with the element 61, and 63 is a buffer amplifier.

  FIG. 19 is a diagram showing addressing of memory cells in the analog FIFO memory according to the present embodiment. In the analog FIFO memory according to the present embodiment, as shown in FIG. 19, so-called vertical addressing is performed in which the memory cells 10 are addressed in a direction perpendicular to the arrangement of the memory cells 10 in the memory bus circuit 1.

  The analog FIFO memory according to this embodiment is the same as that of the first embodiment in that the reset operation is performed before the read operation. What is characteristic in this embodiment is that the operation of resetting the memory bus is performed in parallel with the operation of writing an analog signal. This point will be described.

  If the signal handled by the analog FIFO memory is a video signal, the sampling period of the analog FIFO memory is about 70 ns. Therefore, it is necessary to complete the reset operation of the memory bus and the read operation and write operation of the analog signal in 70 ns. That is, each operation must be completed within about 23 ns. At this time, the GB product required for the operational amplifier used in the write circuit 2 and the read circuit 3 reaches 1 GHz, but this value is very realistic. Not something.

  Therefore, in this embodiment, the reset operation and the write operation are performed in parallel, and then the read operation is performed, so that even when the analog FIFO memory is used for delaying the video signal, about 35 ns for each operation. Allows you to allocate time. As a result, the burden on the operational amplifiers of the write circuit 2 and the read circuit 3 can be reduced, and power consumption can be reduced.

  In order to perform the reset operation and the write operation in parallel, the memory bus must be reset at the same time during which the analog signal is written to the memory cell. However, as a matter of course, since the write operation and the reset operation cannot be executed simultaneously for the same memory bus, in this embodiment, the write operation and the reset operation are performed by adopting the vertical addressing as shown in FIG. Can be executed in parallel. By adopting vertical addressing, an operation of writing an analog signal to one memory bus circuit 1 and an operation of resetting another memory bus circuit 1 can be performed in parallel.

  The operation of the analog FIFO memory according to this embodiment will be described with reference to FIG. The analog FIFO memory shown in FIG. 20 includes four memory bus circuits 1A, 1B, 1C, and 1D, and each switch operates in the order of FIGS. In FIG. 20, the switch that has been turned on is marked with a circle.

  First, as shown in FIG. 20 (a), in the memory bus circuit 1A, the switch of the input means 15 is turned on, the switch of one memory cell 10 is turned on, and this memory cell is turned on. An analog signal is written to 10. On the other hand, in the memory bus circuit 1B from which the analog signal is read next, the switch of the output means 16 is turned on and the switch 32 of the read circuit 3 is also turned on, so that the memory bus 13 of the memory bus circuit 1B is reset. The That is, the write operation for the memory bus circuit 1A and the reset operation for the memory bus circuit 1B are performed in parallel.

  Next, as shown in FIG. 20B, a read operation is performed on the memory bus circuit 1B. Since the switch 32 of the read circuit 3 is turned off and the switch of one memory cell 10 of the memory bus circuit 1B is turned on, an analog signal is read from the memory cell 10 in which the switch is turned on.

  Next, as shown in FIG. 20C, a write operation is performed on the memory bus circuit 1B on which the read operation has been performed. When the switch of the input means 15 of the memory bus circuit 1B is turned on, the switch of one memory cell 10 is turned on, and an analog signal is written in the memory cell 10 in which the switch is turned on. On the other hand, a reset operation is performed on the memory bus circuit 1C from which the analog signal is read next. In the memory bus circuit 1C, the switch of the output means 16 is turned on and the switch 32 of the read circuit 3 is also turned on, so that the memory bus 13 of the memory bus circuit 1C is reset. That is, the write operation for the memory bus circuit 1B and the reset operation for the memory bus circuit 1C are performed in parallel.

  Next, as shown in FIG. 20D, a read operation is performed on the memory bus circuit 1C. Since the switch 32 of the read circuit 3 is turned off and the switch of one memory cell 10 of the memory bus circuit 1C is turned on, an analog signal is read from the memory cell 10 in which the switch is turned on.

  As can be seen from FIG. 20, in the analog FIFO memory according to the present embodiment, by performing addressing on the memory cells vertically, a write operation to one memory bus circuit and a read operation next to the one memory bus circuit are performed. It is possible to perform a reset operation on other memory bus circuits performing the above in parallel. The technical idea according to the present embodiment is that addressing is performed perpendicularly to the memory bus, thereby enabling a write operation and a reset operation to be performed in parallel, and sufficiently securing an operation time in each operation. Thus, the operation speed of the operational amplifier is reduced and the power consumption thereof is reduced.

  Even if vertical addressing is not necessarily employed, when a read operation and a write operation are performed on one of the plurality of memory bus circuits, the memory bus other than the one memory bus circuit is then used. If the address of the memory cell is designated so that the read operation and the write operation are performed on the circuit, the write operation and the reset operation can be performed in parallel as in the present embodiment.

  FIG. 21 is a diagram showing a specific configuration method of the analog FIFO memory according to the present embodiment. In FIG. 21, connection terminals 4a and 4b to the write circuit 2 and connection terminals 5a and 5b to the read circuit 3 are shown, and the write circuit 2 and the read circuit 3 are not shown. As shown in FIG. 21, in order to execute the method according to the present embodiment, a write control unit 71 that generates a signal Sa that drives a write operation, and a read control unit 72 that generates a signal Sb that drives a read operation. The reset control means 73 for generating the signal Sc for driving the reset operation, the first memory bus specifying means 74 for generating the signal SA1 for specifying the memory bus for performing the read operation and the write operation, and the memory bus for performing the reset operation And a second memory bus designation means 75 for generating a signal SA2 for designating.

  FIG. 22 is a timing chart showing the operation of the analog FIFO memory shown in FIG. 21, and shows the time change of the signals Sa, Sb, Sc and the time change of the address of the memory bus designated by the signals SA1, SA2. Here, all the signals are assumed to be low-active.

  The memory bus that performs the reset operation may be a memory bus that always performs the next read operation and write operation. Therefore, the address of the memory bus specified by the signal SA2 generated by the second memory bus specifying means 75 is the memory bus next to the memory bus specified by the signal SA1 generated by the first memory bus specifying means 74. Address.

  The input means 15 of each memory bus circuit 1 is supplied with the switches 15A and 15B by the drive signal Sa generated by the write control means 71 only when addressed by the signal SA1 generated by the first memory bus specifying means 74. Drive. The output means 16 of each memory bus circuit 1 switches the switches 16A and 16B by the drive signal Sb generated by the read control means 72 when addressed by the signal SA1 generated by the first memory bus specifying means 75. On the other hand, when addressed by the signal SA2 generated by the second memory bus specifying means 75, the switches 16A and 16B are driven by the drive signal Sc generated by the reset control means 73.

  By performing the control shown in FIG. 22 in the circuit configuration shown in FIG. 21, each operation shown in FIG. 20 is specifically realized.

(Fourth embodiment)
FIG. 23 is a circuit diagram showing a configuration of an analog FIFO memory according to the fourth embodiment of the present invention. In the fourth embodiment of the present invention, as shown in FIG. 23, in the memory cell circuit 1, a dummy capacitance element 121 is provided in advance between the first and second bus wirings 13A and 13B. A dummy memory cell 120 is configured by the dummy capacitance element 121.

Here, the capacitance value of the dummy capacitance element 121 is Cd, the capacitance value of the inter-wiring capacitance 61 between the first and second bus wirings 13A and 13B is Cp, and the capacitance value of the capacitance element 11 of the memory cell 10 is Cc. The capacitance value of the capacitive element 31 of the circuit 3 is Cc, and the capacitance value of the capacitive element 21 of the write circuit 2 is (Cc + Cd). At this time, assuming that the voltage of the input analog signal is Vin, the charge Q1 stored in the capacitive element 21 of the write circuit 2 is as follows.
Q1 = Vin (Cc + Cd) (7)
In the write operation, the charge Q1 is stored separately in the capacitive element 11, the dummy capacitive element 121, and the inter-wiring capacity 61 of the memory cell 10 according to the capacitance value. At this time, the charge Q2 stored in the capacitive element 11 of the memory cell 10 is as follows.
Q2 = Vin (Cc + Cd) Cc / (Cc + Cd + Cp) (8)

The charges stored in the dummy capacitor 121 and the inter-wiring capacitor 61 other than those stored in the capacitor 11 of the memory cell 10 are not reset by the reset operation of the first and second bus wires 13A and 13B. . For this reason, since the charge transferred to the capacitive element 31 of the read circuit 3 in the read operation is only the charge Q2 stored in the capacitive element 11 of the memory cell 10, the output voltage Vout generated by this charge Q2 is as follows. become.
Vout = Q2 · Cc
= Vin · (Cc + Cd) / (Cc + Cd + Cp)
= Vin / (1 + Cp / (Cc + Cd)) (9)

That is, it can be seen from the equation (9) that the influence of the inter-wiring capacitance 61 on the output voltage Vout is expressed by the following equation.
Cp / (Cc + Cd) (10)
That is, the influence of the inter-wiring capacitance 61 on the output voltage Vout is reduced by the presence of the dummy capacitive element 121. The larger the capacitance value Cd of the dummy capacitive element 121 is, the more the influence of the inter-wiring capacitance 61 on the output voltage Vout is. It turns out that it becomes small.

  As described above, according to the present embodiment, by providing the dummy memory cell having the capacitive element connected to the memory bus, the influence of the parasitic capacitance of the memory bus on the input / output operation of the analog FIFO memory can be reduced. it can.

  This embodiment can obtain a more remarkable effect by combining with the second embodiment. For example, even when an analog FIFO memory is used for delaying a TV signal, the influence of the parasitic capacitance of the memory bus is reduced. Can do.

  As is clear from the equation (10), the larger the capacitance value Cd of the dummy capacitive element 121, the smaller the influence of the interwiring capacitance 61 on the output voltage Vout. However, when the capacitance value Cd of the dummy capacitive element 121 is increased, it is necessary to increase the settling time for transferring charges from the write circuit 2 to the memory cell 10 accordingly. In a conventional analog FIFO memory, for example, when used for delaying a TV signal, it is necessary to operate the circuit at a high speed, so it is actually necessary to increase the settling time when transferring charges from the write circuit 2 to the memory cell 10. It was extremely difficult.

  However, according to the second embodiment, the time allotted for the write operation is doubled compared to the prior art by the parallel operation of the first and second memory units 101a and 101b. The settling time for transferring can be sufficiently large. Therefore, the capacitance value Cd of the dummy capacitive element 121 can be made large enough to reduce the influence of the parasitic capacitance of the memory bus on the input / output operation of the analog FIFO memory.

(Fifth embodiment)
In the fourth embodiment, the influence of the parasitic capacitance of the memory bus is reduced by providing dummy memory cells in the memory bus in advance. In the fifth embodiment of the present invention, the layout position of the dummy memory cell shown in the fourth embodiment is devised, so that the analog FIFO memory is inserted depending on the position of the memory cell to be read and written. This suppresses variations in output characteristics.

  FIG. 24A is a circuit diagram showing a configuration of the memory bus circuit 1 of the analog FIFO memory according to the fifth embodiment of the present invention. In this embodiment, as shown in FIG. 24A, the dummy memory cell 120 shown in the fourth embodiment is divided into two, and the memory cells 10 are arranged at both ends of the memory bus 13 as dummy memory cells 130. Arrange them so that they are pinched. The dummy memory cell 130 includes a dummy capacitance element 131 having the same capacitance value as the capacitance element 11 of the memory cell 10 and a resistance element 132 having the same resistance value as the ON resistance of the switch 12 of the memory cell 10. In the present embodiment, as many dummy memory cells 130 as possible are arranged in parallel at both ends of the memory bus 13.

  FIG. 24B is a diagram showing an equivalent circuit when the switch of one memory cell 10 is turned on in the memory bus circuit 1 shown in FIG. In FIG. 24B, the wiring resistance of the first and second bus wirings 13A and 13B is Rb, and the switch resistance and the capacitance value of each memory cell 10 are R1 and Cm, respectively.

  Since a plurality of memory cells 10 are connected to the memory bus 13, the charge transfer path is physically different depending on which memory cell 10 the charge is transferred to. The change in the impedance of the memory bus 13 is greatest when the position of the memory cell 10 to be read and written changes from the most input side to the most output side of the memory bus 13. A change in impedance of the memory bus 13 at this time is calculated.

Now, it is assumed that (y−1) dummy memory cells 130 are arranged at the input side end of the memory bus 13 and x pieces are arranged at the output side end. When the position of the memory cell 10 to be read and written is the most input side, y memory cells including dummy memory cells 130 are included at the input side end of the memory bus 13 and dummy cells 130 are included at the output side end. That is, x memory cells are connected in parallel. In this case, the impedance Z1 viewed from the input side of the memory bus 13 is as follows.
Z1 = {2Rb · x (R1 + 1 / sCm) + (R1 + 1 / sCm) ² }
/ {2Rb · xy + (x + y) (R1 + 1 / sCm)} (11)

On the other hand, when the position of the memory cell 10 to be read and written is the most output side, (y−1) memory cells including the dummy memory cell 130 at the input side end of the memory bus 13 and the output side end Thus, (x + 1) memory cells including the dummy cell 130 are connected in parallel. Here, if the number of dummy memory cells 130 arranged at the input side end of the memory bus 13 is equal to the number of dummy memory cells 130 arranged at the output side end,
y-1 = x (12)
Therefore, x memory cells including dummy memory cells 130 are connected in parallel to the input side end of the memory bus 13, and y memory cells including dummy cells 130 are connected in parallel to the output side end. The impedance Z2 seen from the input side of the memory bus 13 in this case can be calculated by replacing x and y in the equation (11), and is as follows.
Z2 = {2Rb · y (R1 + 1 / sCm) + (R1 + 1 / sCm) ² }
/ {2Rb · xy + (x + y) (R1 + 1 / sCm)} (13)

Therefore, the impedance change Zc when the position of the memory cell 10 to be read and written changes from the most input side to the most output side of the memory bus 13 is changed from the impedance Z2 shown in the equation (13) to the equation (11). ) Is obtained as follows by subtracting the impedance Z1 shown in FIG.
Zc = 2Rb (R1 + 1 / sCm)
/ {2Rb · xy + (x + y) (R1 + 1 / sCm)} (14)
Here, if R1 >> Rb, Equation (14) is approximated as follows.
Zc = 2Rb / (x + y) (15)
As can be seen from equation (15), the influence of the wiring resistance Rb on the impedance change Zc is reduced to 1 / (x + y). That is, by disposing the dummy memory cells 130 so as to sandwich the memory cells 10 at both ends of the memory bus 13, it is possible to suppress changes in the impedance of the memory bus 13 due to the positions of the memory cells 10 to be read and written. it can.

  As described above, according to the present embodiment, the impedance of the memory bus can be averaged by providing dummy memory cells at both ends of the memory bus, so that the analog FIFO memory according to the position of the memory cell to be read and written is used. Thus, stable input / output characteristics can be realized regardless of the position of the memory cell to be read and written.

(Sixth embodiment)
The sixth embodiment of the present invention relates to a transistor layout for reducing the parasitic capacitance itself of the memory bus.

  FIG. 25 is a diagram for explaining a sixth embodiment of the present invention, in which (a) shows a layout of a conventional transistor, and (b) shows a layout of the transistor according to this embodiment. FIG. 3C is a schematic diagram showing a drain-source capacitance parasitic on a transistor used as a switch of a memory cell.

  In order to reduce the inter-wiring capacitance parasitic on the memory bus, the distance between the memory bus wirings should be as large as possible. However, as shown in FIG. 25C, the drain-source capacitance 146 is inevitably generated in the CMOS transistor 12A constituting the switch 12 of the memory cell 10 in view of the layout. As a result, the inter-wiring capacitance consisting of the series connection of the capacitive element 11 of the memory cell 10 and the drain-source capacitance 146 of the CMOS transistor 12A is parasitic on the memory bus, and the capacitance value of the inter-wiring capacitance is almost equal to the drain- The capacity value of the inter-source capacity 146 is obtained. Such inter-wiring capacitance is not lost unless the drain-source capacitance 146 of the CMOS transistor 12A is eliminated, and such inter-wiring capacitance increases as the number of memory cells 10 increases. When a large number of memory cells 10 are integrated to constitute an analog FIFO memory, it becomes a big problem.

  Therefore, in this embodiment, a transistor layout is proposed in which electric lines of force do not run between the drain and the source. In the first place, a capacity is formed by running lines of electric force from one electrode to another. Therefore, no capacitance is formed unless the electric lines of force run. In this embodiment, paying attention to this point, by laying out the gate electrode between the drain and the source and terminating the electric lines of force generated from the drain and the source on the gate electrode, the electric lines of force run between the drain and the source. This prevents the drain-source capacitance from being formed.

  As shown in FIG. 25A, in the conventional transistor layout, the electric lines of force 145 run between the drain and the source in the portion where the gate electrode 144 between the drain 143 and the source 141 is not disposed. -Capacitance is formed between the sources.

  On the other hand, in the transistor layout according to the present embodiment, as shown in FIG. 25B, the gate electrode 144 is disposed between the drain 143 and the source 141 without any gap, so Running between sources can be prevented. Such a layout prevents the generation of drain-source capacitance.

  As described above, according to the present embodiment, in the CMOS transistor used as the switching element of the memory cell, the drain-source capacitance is prevented from being formed by laying out the layout such that the electric lines of force do not run between the drain-source. can do. As a result, the parasitic capacitance itself parasitic on the memory bus can be reduced.

  The transistor layout according to the present embodiment is not applied only to a transistor used as a switch of a memory cell of an analog FIFO memory, but a transistor used as a switching element that switches and controls a connection state between an element and a signal line. Can be applied, and the same effect as the present embodiment can be obtained.

FIG. 30 is a diagram showing the effect of the reset operation according to the present invention, in which (a) is the frequency characteristic of the analog FIFO memory when the reset operation is not performed, and (b) is the reset operation according to the present invention. It is a frequency characteristic of the analog FIFO memory when it is performed. As can be seen from FIG. 30, by performing the reset operation according to the present invention, the frequency characteristic of the analog FIFO memory becomes flat, and the input / output characteristic of the analog FIFO memory is improved as compared with the conventional case.

It is a figure which shows the analog FIFO memory which concerns on the 1st Embodiment of this invention, (a) is a figure which shows the outline of a structure, (b) is a figure which shows the outline of operation | movement. It is a figure which shows an example of a structure of a memory bus circuit. (A) is a figure which shows an example of a structure of a write circuit, (b) is a figure which shows an example of a structure of a read circuit. It is a figure which shows the structure of the analog FIFO memory which concerns on the 1st Embodiment of this invention, and is a figure which shows the state at the time of reset operation | movement. It is a figure which shows the structure of the analog FIFO memory which concerns on the 1st Embodiment of this invention, and is a figure which shows the state at the time of read-out operation | movement. It is a figure which shows the structure of the analog FIFO memory which concerns on the 1st Embodiment of this invention, and is a figure which shows the state at the time of write-in operation | movement. It is a figure which shows the structure of the read-out circuit which concerns on the modification of the 1st Embodiment of this invention. 1 is a diagram showing a circuit configuration when an analog FIFO memory according to a first embodiment of the present invention has a multiple memory bus configuration. FIG. It is a figure which shows the specific addressing method in the analog FIFO memory provided with the memory cell of m row n column. It is a figure which shows the outline of a structure of the analog FIFO memory based on the 2nd Embodiment of this invention. It is a figure which shows the outline of operation | movement of the analog FIFO memory based on the 2nd Embodiment of this invention shown in FIG. It is a figure which shows the structure of the analog FIFO memory which concerns on the 2nd Embodiment of this invention, and the control signal which controls each switch. It is a figure which shows the time change of each control signal which controls the analog FIFO memory based on the 2nd Embodiment of this invention shown in FIG. It is a figure which shows the state in MODE1 of the analog FIFO memory based on the 2nd Embodiment of this invention shown in FIG. It is a figure which shows the state in MODE2 of the analog FIFO memory based on the 2nd Embodiment of this invention shown in FIG. It is a figure which shows the state in MODE3 of the analog FIFO memory based on the 2nd Embodiment of this invention shown in FIG. It is a figure which shows the state in MODE4 of the analog FIFO memory based on the 2nd Embodiment of this invention shown in FIG. It is a figure which shows the outline of a structure of the analog FIFO memory based on the 3rd Embodiment of this invention. It is a figure which shows the addressing of the analog FIFO memory which concerns on the 3rd Embodiment of this invention. (A)-(d) is a figure which shows operation | movement of the analog FIFO memory based on the 3rd Embodiment of this invention. It is a figure which shows the specific structure of the analog FIFO memory which concerns on the 3rd Embodiment of this invention. FIG. 22 is a timing chart showing the operation of the analog FIFO memory according to the third embodiment of the present invention shown in FIG. 21. It is a figure which shows the structure of the analog FIFO memory which concerns on the 4th Embodiment of this invention. (A) is a figure which shows the structure of the memory bus circuit of the analog FIFO memory based on the 5th Embodiment of this invention, (b) is a switch of one memory cell in the memory bus circuit shown to (a). It is a figure which shows the equivalent circuit when it will be in an ON state. It is a figure for demonstrating the 6th Embodiment of this invention, (a) is a figure which shows the layout of the conventional transistor, (b) is a figure which shows the layout of the transistor which concerns on this embodiment, (c) is FIG. It is a schematic diagram which shows the drain-source capacitance parasitic to the transistor used as a switch of a memory cell. (A) is a figure showing the frequency spectrum of an NTSC color TV signal, (b) is a figure which shows the frequency characteristic of a YC separation filter. (A) is a schematic configuration of a circuit for performing YC separation on an NTSC color TV signal, (b) is a schematic configuration of a TV signal LSI with an external CCD circuit, and (c) is a schematic configuration of a one-chip TV signal LSI. It is a configuration. (A) is a figure which shows the basic composition of the conventional analog FIFO memory, (b) is a timing chart which shows the clock signal which drives the analog FIFO memory shown to (a). It is a figure which shows the outline of operation | movement of the conventional analog FIFO memory. It is a figure which shows the effect of the reset operation | movement which concerns on this invention, (a) is the frequency characteristic of the analog FIFO memory when not performing a reset operation, (b) is an analog FIFO memory when the reset operation which concerns on this invention is performed It is the frequency characteristic.

Explanation of symbols

1, 1A, 1B, 1C, 1D Memory bus circuit 2 Write circuit 3 Read circuit 10 Memory cell 11 Capacitance element 12 Switch 12A MOS transistor 13 Memory bus 13A First bus line 13B Second bus line 15 Input means 16 Output means 31 capacitive element 32 switch 32A first switch 32B second switch 33 operational amplifier 33a reverse phase input terminal 33b positive phase input terminal 33c output terminal 101a first memory unit 101b second memory unit 120 dummy memory cell 121 dummy capacitor Element 130 Dummy memory cell 131 Dummy capacitor element 141 Source 143 Drain 144 Gate 145 Electric field lines

Claims (2)

An analog FIFO memory that delays input analog signals for a predetermined time and outputs them in the order of input,
A memory bus circuit having a plurality of memory cells for storing analog signals and a memory bus connected to each memory cell and transferring the analog signals;
The memory cell includes a capacitive element that accumulates an analog signal in the form of electric charge, and a switch that controls switching of a connection state between the capacitive element and the memory bus, and the switch reads the analog signal. And when it is selected as a target for writing, it is turned on at the time of read operation and write operation,
2. The analog FIFO memory according to claim 1, wherein the memory bus circuit further includes a dummy memory cell having a dummy capacitance element having the same capacitance value as the capacitance element of the memory cell, connected to the memory bus. The analog FIFO memory according to claim 1.
2. The analog FIFO memory according to claim 1, wherein the dummy memory cell is provided so as to sandwich the plurality of memory cells at both ends of the memory bus.

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