JP4230259B2 - Solid-state imaging device, driving method of solid-state imaging device, and camera - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a MOS type solid-state imaging device including a dynamic shift register, and more particularly to improvement of reset operation of the dynamic shift register.
[0002]
[Prior art]
In recent years, attention has been paid to a solid-state imaging device using an amplification type MOS sensor as one of the solid-state imaging devices. This solid-state imaging device amplifies a signal detected by a photodiode for each cell representing a pixel by a transistor, and has a feature of high sensitivity.
[0003]
In such a solid-state imaging device, a dynamic shift register is used as a circuit that horizontally or vertically scans an imaging device having pixels arranged in two dimensions, thereby simplifying the circuit, increasing the density, and reducing power consumption. I am trying.
[0004]
FIG. 6 is a block diagram showing a schematic configuration of a conventional general solid-state imaging device. The solid-state imaging device includes an imaging unit 61 having pixels arranged in two dimensions, a shift register 62 that outputs a row selection signal for selecting one row of the imaging unit 61, and one pixel in the selected row. A shift register 63 that outputs the pixel selection signal, a pixel processing unit 64 that extracts the pixel signal from the selected pixel, and a preamplifier 65 that amplifies the extracted pixel signal.
[0005]
FIG. 7 is a block diagram showing the configuration of an NMOS dynamic shift register, which is used as the shift registers 62 and 63. Although only four stages are shown in the figure, there are actually hundreds to thousands.
[0006]
In the figure, clock signals Clk1 and Clk2 are two-phase clock signals that serve as references for the shift operation. The Clk1 signal is input to the odd-numbered unit register, and the Clk2 signal is input to the even-numbered unit register. Thereby, odd-numbered unit registers and even-numbered unit registers operate alternately.
[0007]
In the figure, Res1, Res2,... (Abbreviated as Res when referring to any one) stores the logical value of the input signal In in synchronization with the clock signal Clk and outputs the stored logical value. It is a unit register that outputs as a signal Out and an output signal Next. The output signal Out is output to the imaging unit 61 as a row selection signal or a column selection signal.
[0008]
Transistors Tr3-1, 3-2,... (Tr3) are reset transistors that reset the input signal In to the unit register. That is, the transistor Tr3 has a low level when the output Out of the unit register at the next stage of the unit register having the input signal In to which the transistor Tr3 is connected is at a low level. The charge accumulated in the storage element in the unit register is discharged to reset the input signal In. If it is not reset, the charge remains in the unit register indefinitely and keeps the high level. After resetting, it becomes low level or high impedance.
[0009]
FIG. 8A is a circuit diagram showing the configuration of the unit register. As shown in the figure, the unit register includes NMOS transistors Tr1 and Tr2 and a capacitor C1. FIG. 8B shows an operation explanatory diagram of the unit register when the input signal In is at a high level. Since the input signal In is at the high level, the gate electrode of the transistor Tr1 is already at the high level due to the gate capacitance of the transistor Tr1 and the potential of the capacitor C1 before the rising edge of the clock signal Clk ((1) in the figure). . In this state, when the clock signal Clk rises from the low level to the high level, the gate voltage In of the transistor Tr1 is boosted (called boot) through the capacitor C1 ((2)). In addition, since a voltage higher than the high level is applied to the gate of the transistor Tr1, the potential under the gate becomes equal to or higher than the high level of the clock (clk), and the high level of the Clk signal is output to the Out signal (same as in (3) above). ▼). When the Clk signal falls, the low level of the Clk signal is output to the Out signal. At this time, the Next signal is output at a high level even after the Clk signal falls because the gate capacitance of the unidirectional transistor Tr2 is maintained at a high level.
[0010]
On the other hand, since the transistor Tr1 is not turned on when the input signal In is at a low level (or floating), both the Out signal and the Next signal remain at a low level (or floating) even when the clock signal Clk is input. is there.
[0011]
FIG. 9 is a time chart showing the shift operation in the shift register. In the figure, clock signals Clk1 and Clk2, input signals (or internal data) In1 to In4, and output signals Out1 to Out4 are the signals shown in FIGS.
[0012]
First, the unit register Res1 boots and holds the high-level input signal In1 in synchronization with the Clk1 signal (1 in the figure) (2). At the same time, the Out1 signal is output as the pixel selection signal (3), and the Next1 signal is set to the high level. The Next1 signal that has become high level is input to the next stage unit register Res2 as an input signal In2. At this time, the other odd-numbered unit registers to which the Clk1 signal has been input have a low level (or high impedance state), and do not capture a high level internally.
[0013]
In this way, the shift operation of the odd-numbered unit register to which the clock signal Clk1 is supplied is performed. The even-numbered unit register is shifted by the next clock signal Clk2.
[0014]
Further, when the output signal Out2 becomes high level, the reset transistor Tr3-1 is turned on and the input signal In1 is set to low level, so that the gate capacitance of the transistor Tr1 in the unit register Res1 and the charge of the capacitor C1 are discharged, The input signal In1 of the unit register Res1 is reset.
[0015]
When the output signal Out3 becomes high level, the reset transistor Tr3-2 is turned on, the gate capacitance of the transistor Tr1 in the unit register Res2 and the capacitor C1 are discharged, and one direction in the unit register Res1 is passed through the Next1 signal line. The charge of the gate capacitance of the conductive transistor Tr2 is also discharged. As a result, the input signal In2 of the unit register Res2 is reset.
[0016]
In this way, in the NMOS type dynamic shift register, the unit register that outputs a high level resets the input signal In to the unit register in the previous stage.
There is Patent Document 1 as a prior art of such a shift register. Patent Document 1 discloses a bidirectional shift register in which a shift direction can be selected by providing a transistor group that connects unit registers in the forward direction and a transistor group that connects in the reverse direction.
[0017]
[Patent Document 1]
Japanese Patent Laid-Open No. 64-44178
[Problems to be solved by the invention]
By the way, according to the shift register in the above prior art, since the input signal of the previous unit register is reset by the output Out of the subsequent unit register, the input signal of the final unit register must be reset in the same way. Therefore, resetting the input signal to the unit register in the final stage must be handled separately.
[0019]
As an example of resetting the input signal to the unit register at the final stage, there is a configuration in which a unit register for reset is further added after the final stage, and an all clear function to reset the input signal to all unit registers. There is a configuration in which the final stage reset is performed by all clear, and the above-described Patent Document 1 is considered to have the same configuration.
[0020]
However, these all require a simple reset method in that they include redundant configurations.
In view of the above problems, an object of the present invention is to provide a solid-state imaging device, a solid-state imaging device method, and a camera including a shift register that resets an input signal at the final stage of a unit register with a simple configuration.
[0021]
[Means for Solving the Problems]
In order to solve the above problems, a solid-state imaging device according to the present invention is a solid-state imaging device having a shift register for sequentially selecting rows or columns of imaging elements formed by a dynamic logic circuit and arranged two-dimensionally. The shift register is provided in a plurality of unit registers for holding signals and a unit register in the final stage, and an input signal to the unit register in the final stage using an output signal of one or more previous stage registers from the last stage And a second reset circuit for resetting. In this configuration, the final stage reset circuit may be configured to reset an input signal to the final stage unit register using an output signal from the previous stage unit register to the previous stage unit register. For example, the final stage unit register is reset by the final stage reset circuit. In addition, since the final stage reset circuit uses the output signal of the unit register one or more stages before the final stage, it is not necessary to provide an extra unit register, and it is not necessary to provide a circuit for simultaneously resetting all the unit registers. With this configuration, the unit register at the final stage can be reset reliably.
[0022]
Here, the final stage reset circuit is provided between the final stage unit register and the previous stage unit register, and is turned on and off by an operation clock having a phase different from that of the final stage operation clock; It is also possible to have an inverter that inverts the output signal of the unit register of one or more previous stages and a reset transistor that is turned on by the inverter output to bring the final stage input to a low level via the transistor.
[0023]
According to this configuration, since the final stage reset circuit includes two transistors and one inverter, the reset of the final stage unit register can be realized with a simple configuration.
[0024]
Here, the final stage reset circuit resets an input signal to the final stage unit register using an output signal from the previous stage unit register of the final stage to the previous stage unit register. The signal reset circuit provided may be configured to reset the output signal from the unit register in the last stage of the last stage to the unit register in the previous stage in accordance with the output signal of the unit register in the last stage.
[0025]
According to this configuration, in the first reset circuit provided in the final stage unit register, the input signal to the previous stage unit register is reset by the output signal of the final stage unit register, and then the final stage unit register is reset. Since the final stage is reset in the reset circuit, there is an effect that the unit register in the final stage can be surely reset immediately after the output signal of the final stage is output and the shift operation is completed.
[0026]
The driving method and camera of the solid-state imaging device of the present invention also have the same means, actions, and effects as described above.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a configuration of a shift register in the embodiment of the present invention. This shift register is provided as either or both of a shift register 62 that outputs a row selection signal and a shift register 63 that outputs a pixel selection signal in the camera including the solid-state imaging device shown in FIG. Although only four stages are shown in FIG. 1 for convenience, there are actually hundreds to thousands depending on the number of pixels.
[0028]
As shown in FIG. 1, the shift register includes unit registers Res1, Res2,..., Transistors Tr3-1, Tr3-2... (Abbreviated as Tr3 when referring to any one), a transistor Tr6, The inverter 11 is provided, and the final stage input signal is reset by the transistor Tr6 and the output of the inverter 11.
[0029]
The unit register Res stores the logical value of the input signal In in synchronization with the clock signal Clk, and outputs the stored logical values as the output signal Out and the output signal Next. Here, the logical value is one of two states of high level and floating, or one of two states of high level and low level. However, since the voltage appearing in the input signal In is booted inside the unit register, it temporarily becomes higher than the high level. The individual configuration of the unit register res is the same as that shown in FIG. 8A, and the internal operation timing is also the same as that shown in FIG.
[0030]
Transistors Tr3-1, 3-2, 3-3,... (Tr3) are reset transistors that reset the input signals In1, In2, In3,. For example, the transistor 3-2 has the gate capacitance of the transistor Tr1 in the unit register Res2 connected to the input signal In2 by setting the input signal In2 to low level when the output Out3 of the unit register Res3 is high level. The charge of the capacitor C1 is discharged, and the charge of the gate capacitance of the transistor Tr2 in the unit register Res1 is discharged. If it is not reset, the charge remains in the unit register indefinitely and continues to output a high level. In the next clock signal that has been reset, the output signals Out and Next become a low level output or a high impedance. Note that the transistor Tr3-1 may be omitted when the input signal In1 to which the start pulse is input takes two states of high level and low level instead of two states of high level and floating.
[0031]
The transistor Tr3-4 is turned on when the output of the inverter 11 is at a high level, and in the on state, the transistor Tr3-4 outputs a low level to the Next signal of the unit register Res3 and the In signal of the unit register Res4 at the final stage via the transistor Tr6. This is a reset transistor for resetting the input signal In to the unit register.
[0032]
The transistor Tr6 is turned on when the clock signal Clk1 is at a high level. As a result, when the clock signal Clk1 is at a high level and the output of the inverter 11 is at a high level, the input signal to the unit register at the final stage is reset. In other words, the transistor Tr6 is provided for resetting the input In of the unit register at the final stage after the output of the output signal Out4 is completed when the output of the inverter 11 becomes high level.
[0033]
The inverter 11 uses the output signal Next2 of the unit register two stages before the final stage as the input signal InvIN, and outputs an output signal InvOut whose logic value is inverted to the reset transistor tr3-4.
[0034]
FIG. 2A is a diagram illustrating a circuit example of the inverter 11. As shown in FIG. 6A, the inverter 11 is composed of a pull-up resistor R1 and a transistor Tr11. If the input signal InvIN is low level, the transistor Tr11 is turned off, so the high level from the pull-up resistor R1 is output as the output signal InvOut. If the input signal InvIN is high level, the transistor Tr11 is turned on, so the transistor Tr11 To output a low level as an output signal InvOut.
[0035]
The circuit example of the inverter 11 may be the circuit example of FIG. 5B instead of FIG. The circuit example of FIG. 7B includes a transistor Tr12 instead of the pull-up resistor R1 as compared with FIG. If the input signal InvIN is at a low level, the transistor Tr11 is turned off and the transistor Tr12 is turned on so that a high level is output as the output signal InvOut. If the input signal InvIN is at a high level, the transistor Tr11 is turned on and the transistor Tr12 Since is turned off, the low level is output as the output signal InvOut.
[0036]
FIG. 3 is a time chart showing the operation timing of the shift register shown in FIG. In the figure, clock signals Clk1 and Clk2, input signals (or internal data) In1 to In4, InvIn signal, InvOut signal, and output signals Out1 to Out4 are the signals shown in FIG.
[0037]
In the figure, the reset of the input signal In to the unit registers other than the final stage unit register Res4 is the same as that of FIG.
[0038]
When the output signal Out4 of the final stage unit register Res4 becomes high level, the transistor 3-3 is turned on to discharge the gate capacitance of the unidirectional transistor Tr2 in the unit register Res2, and the output signal of the unit register Res2 Next2 (ie, InvIN) becomes low level ((1) in FIGS. 3 and 1). As a result, the output signal InvOut of the inverter 11 becomes high level (2), and the reset transistor Tr3-4 is turned on.
[0039]
By turning on the reset transistor Tr3-4, the capacitance component of the unidirectional transistor Tr2 in the unit register Res3 is reset, but since the transistor Tr6 is off, the unit register Res4 in the final stage is not yet reset. At this timing (2), the transistor Tr6 is off because the clock signal Clk1 is at a low level. If the transistor Tr6 is on, the transistor Tr6 is reset as soon as the output signal Out4 rises. It is.
[0040]
Further, when the high level period of the output signal Out4 ends and the clock signal Clk1 becomes high level, the transistor Tr6 is turned on, so that the unit register Res4 in the final stage is reset from the reset transistor Tr3-4 via the transistor Tr6. (3).
[0041]
As described above, the unit register input signal of the final stage is generated by the inverter 11 that inverts the next signal of the unit register two stages before, the reset transistor Tr3-4, and the transistor Tr6 that adjusts the reset timing by the clock signal Clk1. The output signal Out4 is reset after it falls normally. As a result, a pulse of the output signal is output from the last stage unit register, that is, immediately after the shift operation of the shift register is completed, the input signal to the last stage unit register is reset.
[0042]
As described above, according to the shift register in this embodiment, the input signal to the unit register at the final stage can be reset by a simple reset circuit including one inverter and two transistors. Since the inverter corresponds to one or two transistors as shown in FIG. 2, the reset circuit can be realized by a circuit corresponding to three or four transistors.
[0043]
For a bidirectional shift register such as that disclosed in Patent Document 1, the reset circuit in the above embodiment is provided in two locations: the last stage unit register in the forward shift and the last stage unit register in the backward shift. The configuration may be provided.
[0044]
FIG. 4 is a diagram illustrating a configuration of a shift register according to another embodiment.
The shift register of FIG. 6 differs from that of FIG. 1 in that transistors Tr6-1 to Tr6-3 are added to the input signal In to the unit registers other than the final stage. The transistors Tr6-1 to Tr6-3 are provided to limit the load capacity of the input signal In viewed from the unit register to one transistor Tr6 and to prevent the boot voltage in the unit register from being lowered. In this case, for example, when the transistor that inputs the register signal of the previous stage and the transistor that inputs the register signal of the subsequent stage are connected to one unit register like the above-described bidirectional shift register, the transistor Tr6 By connecting to the input of the unit register via the terminal, it is possible to prevent the load capacity from increasing. As a result, it is possible to prevent the boot voltage from being lowered.
[0045]
Furthermore, FIG. 5 is a block diagram showing a configuration of a shift register in another embodiment. In the shift register shown in FIG. 1 and FIG. 4, the input signal of the last unit register is reset using the output signal of the last stage, whereas in the shift register shown in FIG. The example of a structure which resets using the output signal (Next) of the front | former stage is shown.
[0046]
【The invention's effect】
According to the present invention, it is not necessary to provide an extra unit register for reset at the next stage of the shift register, and it is not necessary to provide a circuit for resetting all the unit registers at the same time. There is an effect that it can be surely reset.
[0047]
Further, immediately after the output signal of the final stage is output and the shift operation is completed, the unit register of the final stage can be surely reset.
Further, a reset circuit for the unit register in the final stage can be realized with a simple configuration of two transistors and one inverter.
[0048]
Further, the driving method and the camera of the solid-state imaging device of the present invention have the same effects as described above.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a shift register in an embodiment of the present invention.
FIG. 2A is a diagram illustrating a circuit example of an inverter.
(B) It is a figure which shows the other circuit example of an inverter.
FIG. 3 is a time chart showing the operation timing of the shift register.
FIG. 4 illustrates a structure of a shift register in another embodiment.
FIG. 5 is a diagram showing a configuration of a shift register in still another embodiment.
FIG. 6 is a block diagram illustrating a schematic configuration of a solid-state imaging device.
FIG. 7 is a block diagram showing a configuration of a conventional NMOS dynamic shift register.
FIG. 8A is a circuit diagram showing a configuration of a unit register.
(B) It is a time chart which shows the operation timing of a unit register.
FIG. 9 is a time chart showing a shift operation in a conventional shift register.
[Explanation of symbols]
11 Inverter 61 Imaging unit 62 Shift register 63 Shift register 64 Signal processing unit 65 Preamplifier
Res1 to Res4 unit register
Tr1 transistor
Tr2 transistor
Tr3-1 to Tr3-4 transistors
Tr6-1 to Tr6-4 transistors
Tr11 transistor
Tr12 transistor
C1 capacitor

Claims (8)

A solid-state imaging device having a shift register for sequentially selecting rows or columns of imaging elements formed by a dynamic logic circuit and arranged two-dimensionally,
The shift register is
A multi-stage unit register for holding a signal;
Have a final stage reset circuit using the output signal of the previous unit register more than one stage from the last stage to reset the input signal to the unit register in the final stage,
The final stage reset circuit includes:
A transistor provided between the unit register of the last stage and the unit register of the preceding stage, and turned on and off by an operation clock having a phase different from that of the operation clock of the last stage;
An inverter that inverts the output signal of the unit register in the preceding stage one or more stages in the final stage
A reset transistor that turns on the final stage input through the transistor by turning on the inverter output; and
The solid-state imaging device characterized in that it comprises a. The said last stage reset circuit resets the input signal to the unit register of the last stage using the output signal from the unit register of the last stage before the last stage to the unit register of the preceding stage. Solid-state imaging device. The solid-state imaging device further includes:
3. The solid-state imaging device according to claim 1, further comprising a signal reset circuit that resets a signal to one or more previous stage unit registers of the unit register using an output signal of each unit register. The signal reset circuit is:
The solid-state imaging device according to claim 3 , wherein an output signal from the preceding stage to the preceding stage of the unit register is reset using an output signal of each unit register. A driving method of a solid-state imaging device having a shift register for sequentially selecting rows or columns of imaging elements formed by a dynamic logic circuit and arranged two-dimensionally,
The shift register has a multi-stage unit register for holding a signal,
The driving method is:
Possess a final stage reset step of resetting an input signal to the unit register in the final stage by using an output signal of the previous unit register more than one stage from the last stage,
In the final stage reset step, the input signal to the final stage unit register is reset using the output signal from the previous stage unit register to the previous stage unit register in the final stage,
The shift register includes a transistor that is provided between a unit register at the last stage and a unit register at the preceding stage and that is turned on and off by an operation clock having a phase different from that of the operation clock at the last stage, and an output before the last stage. A final stage reset circuit comprising an inverter that inverts the signal and a reset transistor that turns on the final stage input through the transistor by turning on the inverter output;
In the final stage reset step, an input signal to the final stage unit register is reset by the final stage reset circuit . The driving method further includes:
The driving method according to claim 5, further comprising: a signal reset step of resetting a signal to a unit register at one or more stages before the unit register using an output signal of the unit register that outputs a high level. The driving method according to claim 6 , wherein, in the signal reset step, an output signal from the previous stage to the previous stage of the unit register is reset using an output signal of the unit register that outputs a high level. A camera comprising the solid-state imaging device according to claim 1 .

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