JPH1093864A - Driving method for mos-type solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOS-type solid-state image pickup device without the occurrence of shading and the like on a reproduced screen. SOLUTION: Potential for reading a signal charge accumulated in a unit cell is applied (t=1) to the horizontal address line of a read line among horizontal address lines for selecting the unit cell of the line for reading a signal from the unit cell accumulating the signal charge. Potential for resetting the charge accumulated in the unit cell of the read line is applied (t=3) to a reset line. The potential of the horizontal address line of the read line is changed and the charge accumulated in the unit cell of the read line is reset (t=4).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a MOS solid-state imaging device.

[0002]

2. Description of the Related Art In recent years, various amplification type solid-state imaging devices have been proposed as one of MOS type solid-state imaging devices. FIG.
FIG. 1 is a circuit diagram showing an outline of such a MOS solid-state imaging device.

As shown in FIG. 1, a unit cell of this MOS type solid-state image pickup device includes a photodiode 1 (1-1-1 to 1-1-1).
1-2-2), photodiode 1 (1-1-1 to 1--1)
2-2) Amplifying transistor 2 (2-1) for amplifying the signal
-1 to 2-2-2), an address capacitor 3 (3-1-1 to 3-2-2) for selecting a line from which a signal is read, and a reset transistor 4 (4-1-1 to 4-1) for resetting a signal charge.
4-2-2).

[0006] Here, a diagram in which 2 × 2 unit cells are arranged two-dimensionally is shown, but actually more unit cells are arranged. Vertical shift register 5
From the horizontal address line 6 (6-
1, 6-2) is address capacity 3 (3-1-1 to 3-2-2).
The line connected to 2) for reading out the signal is determined.

The reset line 7 (7-1, 7-2) is connected to the gate of the reset transistor 4 (4-1-1 to 4-2-2). Amplification transistor 2 (2-1-1)
To 2-2-2) are the vertical signal lines 8 (8-1, 8-).
Connected to 2).

A load transistor 9 (9-1, 9-2) is connected to one end of the vertical signal line 8 (8-1, 8-2), and one line (one row) is connected to the other end. Signal capturing transistor 10 (10-1, 10-
2), is connected to an amplified signal storage capacitor 11 (11-1, 11-2) for storing one line (one row) of signals, and is selected by a selection pulse supplied from the horizontal shift register 13. Horizontal selection transistor 12
It is connected to the horizontal signal line 15 via (12-1, 12-2).

Hereinafter, the operation of the MOS type solid-state imaging device will be described with reference to a timing chart of FIG. When an address pulse 21-1 for setting the horizontal address line 6-1 to a high level is applied, the amplification transistors 2-1-1 and 2-1-2 and the load transistors 9-1 and 9-1 in this row are applied.
9-2 constitutes a source follower circuit.

As a result, the amplification transistor 2-1
Gate voltages of 1, 1-2-2, that is, voltages substantially equal to the voltages of the photodiodes 1-1-1, 1-1-2 appear on the vertical signal lines 8-1, 8-2.

At this time, the signal capturing transistor 10
A signal capture pulse is applied to the common gates 14-1 and 10-2, and the voltages appearing on the vertical signal lines 8-1 and 8-2 and the products of the capacitances are applied to the amplified signal storage capacitors 11-1 and 11-2. The amplified signal charge is stored.

After the signals are stored in the amplified signal storage capacitors 11-1 and 11-2, the reset transistors 4-1-1 and 4-1-1 are reset.
A reset pulse 22-1 is applied to 4-1-2 to reset signal charges accumulated in the photodiodes 1-1-1 and 1-1-2.

FIG. 10 is a potential distribution diagram showing the operation of the reset transistor at this time. As shown in the figure,
When a reset pulse is applied to the reset transistor, the detector 16-1 on the source side of the reset transistor
The electric charge accumulated in the drain flows to the drain side to be reset.

Next, horizontal selection pulses 23-1 and 23-2 are sequentially applied from the horizontal shift register 13 to the horizontal selection transistors 12-1 and 12-2, and one row of output signals 24- Take out 1,4-2-2 sequentially.
By continuing this operation sequentially from the next line to the next line, all the signals of the photodiodes arranged two-dimensionally can be read.

[0013]

However, such a MOS solid-state imaging device has the following problems. That is, the reset transistor 4 is normally
Since the transistor is constituted by an S-type transistor, the reset line serving as a gate of the MOS transistor is formed of polycrystalline silicon.

Since the reset of the cell detection unit is performed commonly in the selected row, the reset line 7 is a long wiring extending in the row direction. However, the size of the unit cell has been gradually reduced due to the recent demand for a larger number of pixels. Therefore, the wiring width of the polycrystalline silicon wiring is becoming smaller year by year, and the wiring resistance tends to be higher.

On the other hand, as the unit cell becomes finer, the thickness of the insulating film also tends to be thinner, so that the capacitance between wirings also tends to increase year by year. When the resistance of the wiring increases and the capacitance between the wirings increases, the transmission time constant of the wiring determined by the product of the wiring resistance and the capacitance between the wirings increases. When the transmission time constant of the wiring increases, the time required for the voltage of the pulse applied from the power supply to the reset line to be sufficiently transmitted to a portion farther from the power supply increases.

When the transmission time becomes substantially equal to the time width of the pulse to be applied, the pulse voltage is not sufficiently transmitted to a portion farther from the power source, and as a result,
There is a problem that shading or the like occurs on the playback screen.

The present invention has been made in view of the above circumstances, and has as its object to provide a method of driving a MOS type solid-state imaging device which does not cause shading or the like on a reproduction screen.

[0018]

Therefore, to achieve the above object, a first aspect of the present invention is to provide a horizontal address line for selecting a unit cell in a row from which a signal is read out from a unit cell in which signal charges are stored. A first potential is applied to the horizontal address line of the readout row to read out signal charges accumulated in the unit cell, and a second potential higher than the first potential is applied to the horizontal address line of the readout row Is applied to a reset line for resetting the electric charge accumulated in the unit cell of the readout row, and the potential of the horizontal address line of the readout row is changed from the second potential to the second potential. The first potential is restored, and charges accumulated in the unit cells of the readout row are reset by a third potential applied to the reset line.

According to a second aspect of the present invention, among the horizontal address lines for selecting a unit cell of a row from which a signal is read out from a unit cell in which signal charges are stored, a first potential is applied to the horizontal address line of the readout row. To apply a second potential to a reset line for reading out signal charges stored in the unit cells and resetting the charges stored in the unit cells in the readout row, and applying a horizontal address to the readout row. A third potential lower than the first potential is applied to a line, and charges accumulated in unit cells of the readout row are reset by a second potential applied to the reset line.

Further, according to a third aspect of the present invention, a potential is applied to the horizontal address line of a readout row among horizontal address lines for selecting a unit cell of a row from which a signal is read out from a unit cell in which signal charges are stored. And reading out the signal charges stored in the unit cells, resetting the charges stored in the unit cells in the readout row by changing the potentials to a potential lower than the potential of the horizontal address line in the readout row.

Next, the operation of the first to fourth inventions will be described. First, in the first invention, a signal potential stored in a unit cell is read by applying a first potential to a horizontal address line of a read row. Next, after a second potential higher than the first potential is applied to the horizontal address line of the read row,
A third potential for resetting the charge stored in the unit cell of the reading row is applied to the reset line.

Then, the potential of the horizontal address line of the read row is returned from the second potential to the first potential, and the electric charge accumulated in the unit cell of the read row is reset by the third potential applied to the reset line. Therefore, the charges of the unit cells in the readout row can be reset at the same time, and as a result, it is possible to prevent a problem such as shading from occurring on the reproduction screen.

According to a second aspect of the present invention, among the horizontal address lines for selecting a unit cell in a row from which a signal is read out from a unit cell in which signal charges are stored, a first potential is applied to the horizontal address line in a readout row. To read out the signal charges stored in the unit cell.

Next, a second potential for resetting the charge stored in the unit cell of the readout row is applied to the reset line. Then, a third potential lower than the first potential is applied to the horizontal address line of the readout row, and the charges accumulated in the unit cells of the readout row are reset by the second potential applied to the reset line. Therefore, the charges of the unit cells in the readout row can be reset at the same time, and as a result, it is possible to prevent a problem such as shading from occurring on the reproduction screen.

Further, according to a third aspect of the present invention, a potential is applied to the horizontal address line of a readout row among horizontal address lines for selecting a unit cell of a row from which a signal is read out from a unit cell storing signal charges. To read the signal charges stored in the unit cell.

Then, the electric charges stored in the unit cells of the read row are reset by changing the electric potential to a potential lower than the potential of the horizontal address line of the read row. Therefore, the electric charges of the unit cells of the read row can be simultaneously reset. As a result, it is possible to prevent problems such as shading from occurring on the playback screen.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> The difference between the MOS-type solid-state imaging device of the present embodiment and a conventional MOS-type solid-state imaging device lies in a method of driving a unit cell.

FIG. 1 is a diagram showing a configuration of one unit cell of a MOS type solid-state imaging device. Here, although the configuration of the unit cell in the first row and the first column is shown, the configuration of the other unit cells has the same configuration as in FIG. Note that the same parts as those in FIG.

FIG. 3 is a timing chart showing the operation of the MOS type solid-state imaging device according to the first embodiment of the present invention. Hereinafter, based on this timing chart,
The operation of the MOS solid-state imaging device according to the present embodiment will be described.

First, the horizontal address line of the selected row, that is, the horizontal address line 6-1 of the first row and first column in this case, is set to the selected potential by the vertical shift register 5 during one horizontal blanking period (t = 1). As a result, the signal accumulated in the detection unit 16-1 is read out to the vertical signal line 8-1 via the amplification transistor 2-1-1, and the amplified signal accumulation capacitance 11-
1 is stored.

The stored signals are read out to the horizontal signal line 15 by sequentially turning on the horizontal shift register 13. Next, by the vertical shift register 5,
The horizontal address line 6-1 is set to a potential higher than the selection potential (t = 2). Subsequently, a reset pulse is applied to the reset line 7-1 (t = 3), and thereafter, the address line 6-1 is returned to the row selection potential (t = 4).

By continuing this operation sequentially from the next line to the next line, all the signals of the photodiodes arranged two-dimensionally can be read. FIG. 2 is a potential distribution diagram showing the operation of the reset transistor 4-1-1 at each operation timing of the MOS solid-state imaging device according to the present embodiment.

First, in a state where a pulse of a row selection potential is applied to the address line 6-1 of the selected row (t = 1), the potential of the detection unit 16-1 is set high by the address capacitance 3-1-1. It becomes higher on the potential side. As a result, the signal accumulated in the detection unit 16-1 is read out to the vertical signal line 8-1 via the amplification transistor 2-1-1.

Next, since the horizontal address line 6-1 is set to a potential higher than the row selection potential, the potential of the detector 16-1 changes to a higher potential (t = 2). Subsequently, a reset pulse is applied to the reset line 7-1 (t =
3) At this time, since the potential of the detection unit 16-1 corresponding to the source potential of the reset transistor is sufficiently high, no current flows through the reset transistor 4-1-1.

When a current flows through the reset transistor 4-1-1, the capacitance of the reset transistor becomes the gate oxide film capacitance.
The capacitance between the substrate and the substrate becomes extremely large.

However, in the MOS type solid-state imaging device of the present embodiment, the reset transistor 4-1
Since no current flows when 1 is turned on, the reset line 7
The capacitance between -1 and the substrate is a series capacitance between the gate oxide film capacitance and the substrate depletion layer capacitance, and the capacitance connected to the reset line 7-1 is much smaller. Therefore, the transmission time of the reset line 7-1 becomes sufficiently short. As a result, the potential of the reset line 7-1 becomes the same as the potential of other portions even in a portion far from the power supply line, and a problem such as shading occurs. (T = 3).

Subsequently, the potential of the horizontal address line 6-1 returns to the row selection potential (t = 4). At this time, since the potential of the detection unit, which is the source of the reset transistor 4-1-1, decreases, a current flows through the reset transistor 4-1-1.
The detection unit 16-1 is reset.

Therefore, according to the MOS type solid-state imaging device of the present embodiment, when turning on the gate of the reset transistor, a potential higher than the row selection potential is applied to the address line so that no current flows through the reset transistor. Since the voltage is applied, the capacitance between the reset transistor and the substrate is sufficiently small, and the reset transistor located far from the power supply is turned on at substantially the same time.

Then, after all the reset transistors are completely turned on, the potential of the address line is returned to the row selection potential for resetting, so that the occurrence of problems such as shading on the reproduction screen is suppressed. be able to. <Second Embodiment> FIG. 4 is a timing chart showing the operation of a MOS solid-state imaging device according to a second embodiment of the present invention. Hereinafter, the operation of the MOS-type solid-state imaging device according to the present embodiment will be described based on this timing chart. The circuit configuration is the same as in FIG.
In addition, the same parts as those in FIG.

First, the horizontal address line of the selected row, here, the horizontal address line 6-1 of the first row and the first column, is set to the selection potential by the vertical shift register 5 during one horizontal blanking period (t = 1). This selection potential is a potential at which no current flows through the reset transistor. As a result, the signal accumulated in the detection unit 16-1 is read out to the vertical signal line 8-1 via the amplification transistor 2-1-1,
It is stored in the amplified signal storage capacitor 11-1.

The stored signals are read out to the horizontal signal line 15 by sequentially turning on the horizontal shift register 13. Next, by the vertical shift register 5,
A reset pulse is applied to the reset line 7-1 (t
= 2) At this time, since the potential of the detection unit 16-1 corresponding to the source potential of the reset transistor is sufficiently high, no current flows through the reset transistor. Subsequently, the horizontal address line 6-1 is set to a potential lower than the selection potential by the vertical shift register 5 (t = 3). This allows
The charge is reset.

Thereafter, the address line 6-1 is returned to the row selection potential, and the potential of the reset transistor 4-1-1 is returned (t = 4). Thus, the reset operation is completed.

By continuing this operation sequentially with the next line, all signals of the photodiodes arranged two-dimensionally can be read. FIG. 5 is a potential distribution diagram illustrating the operation of the reset transistor 4-1-1 at each operation timing of the MOS solid-state imaging device according to the present embodiment.

First, in a state where a pulse of a row selection potential is applied to the address line 6-1 of the selected row (t = 1), the potential of the detection unit 16-1 is set high by the address capacitance 3-1-1. It becomes higher on the potential side. As a result, the signal accumulated in the detection unit 16-1 is read out to the vertical signal line 8-1 via the amplification transistor 2-1-1.

Next, a reset pulse is applied to the reset line 7-1 (t = 2). At this time, since the potential of the detecting section 16-1 corresponding to the source potential of the reset transistor is sufficiently high, the reset pulse is applied. No current flows through the transistor 4-1-1.

Next, since the horizontal address line 6-1 is set to a potential lower than the row selection potential, the potential of the detector 16-1 changes to a lower potential (t = 3). At this time, a current flows through the reset transistor 4-1-1, and the detection unit 16-1 is reset.

Next, the potential of the horizontal address line 6-1 is returned to the row selection potential (t = 4), and the reset operation ends.
In the MOS solid-state imaging device according to the present embodiment, there are some modified examples, in which a reset pulse is not applied to a reset line as shown in FIG. 6 or a reset is performed as shown in FIG. For example, when the address line potential at this time is made equal to the non-selection potential, the present invention can be modified without changing the gist of the present invention.

Therefore, according to the MOS solid-state imaging device of the present embodiment, when the gate of the reset transistor is turned on, a high potential is applied to the address line so that no current flows through the reset transistor. , The capacitance between the reset transistor and the substrate is small enough,
The reset transistors located far from the power supply are also turned on at substantially the same time.

Then, after all the reset transistors are completely turned on, reset is performed by setting the potential to a potential lower than the potential of the address line. Therefore, the occurrence of problems such as shading on the reproduction screen is suppressed. Can be.

[0050]

As described above in detail, according to the present invention,
It is possible to provide a driving method of a MOS solid-state imaging device in which shading or the like does not occur on a reproduction screen.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of one unit cell of a MOS solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a potential distribution diagram showing an operation of a reset transistor at each operation timing of the MOS solid-state imaging device according to the first embodiment.

FIG. 3 is a timing chart showing an operation of the MOS solid-state imaging device according to the first embodiment;

FIG. 4 is a timing chart showing an operation of a MOS solid-state imaging device according to a second embodiment of the present invention.

FIG. 5 is a reset transistor 4-1 at each operation timing of the MOS solid-state imaging device according to the embodiment;
FIG. 3 is a potential distribution diagram illustrating an operation of −1.

FIG. 6 is a timing chart showing a first modification of the control method of the MOS solid-state imaging device according to the embodiment;

FIG. 7 is a timing chart showing a second modification of the control method of the MOS solid-state imaging device according to the embodiment;

FIG. 8 is a diagram showing a circuit configuration of a conventional MOS-type solid-state imaging device.

FIG. 9 is a timing chart for explaining the operation of a conventional MOS solid-state imaging device.

FIG. 10 is a potential distribution diagram illustrating an operation of a reset transistor.

[Explanation of symbols]

1-1-1, 1-1-2, ..., 1-2-2 ... photodiode, 2-1-1, 1-2-1, ..., 2-2-2 ... amplification transistor, 3-1 1, 3-1-2, ..., 3-2-2 ... address capacity, 4-1-1, 4-1-2, ..., 4-2-2 ... reset transistor, 5 ... vertical shift register, 6- 1, 6-2: horizontal address line, 7-1, 7-2: reset line, 8-1, 8-2: vertical signal line, 9-1, 9-2: load transistor, 10-1, 10- 2 ... Signal taking-in transistor, 11-1, 11-2 ... Amplified signal storage capacity, 12-1, 12-2 ... Horizontal selecting transistor, 13 ... Horizontal shift register, 14 ... Common gate of signal taking-in transistor, 15 ... Horizontal signal Line, 16-1: detecting section, 21: address pulse, 22: reset pulse, 3 ... horizontal selection pulse, 24 ... output signal.

Claims (3)

[Claims] 1. A method of selecting a unit cell in a row from which a signal is read out from a unit cell in which a signal charge is stored, by applying a first potential to the horizontal address line in the readout row and applying the first potential to the unit cell To read a signal charge stored in the readout row, apply a second potential higher than the first potential to the horizontal address line of the readout row, and reset the charge stored in the unit cell of the readout row. Is applied to the reset line, the potential of the horizontal address line of the readout row is returned from the second potential to the first potential, and the readout is performed by the third potential applied to the reset line. MOS resetting electric charges accumulated in a unit cell in a row
For driving a solid-state imaging device. 2. A unit cell, comprising: applying a first potential to the horizontal address line of a readout row among horizontal address lines for selecting a unit cell of a row from which a signal is read out from a unit cell storing signal charges; A second potential for resetting the charges stored in the unit cells of the readout row is applied to a reset line, and the first address is applied to a horizontal address line of the readout row. Driving a MOS-type solid-state imaging device, wherein a third potential lower than a potential is applied, and charges accumulated in unit cells of the readout row are reset by a second potential applied to the reset line. Method. 3. A horizontal address line for selecting a unit cell in a row from which a signal is read out from a unit cell in which a signal charge is stored, and applying a potential to the horizontal address line in the readout row to store the signal charge in the unit cell. A method for driving a MOS solid-state imaging device, comprising: reading out a signal charge that has been read out, changing the potential to a potential lower than the potential of a horizontal address line in the readout row, and resetting the charge stored in a unit cell in the readout row .