JPH0432096A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To execute a read-out operation by the data rate of a higher speed than that of a conventional semiconductor memory by cascading and providing a switch circuit on one or plural cascade connection points of sense amplifiers which are subjected to cascade connection. CONSTITUTION:In the semiconductor memory having plural sense amplifiers which are subjected to cascade connection, as a data read-out circuit part, a switch circuit is installed between the sense amplifiers which are subjected to cascade connection. That is, the switch circuit 101 is installed between the sense amplifier 111 of an initial stage for sensing a read-out data signal from a memory cell and the sense amplifier 121 of a final stage for driving an output buffer 141. In such a state, by a relation to sense amplifier control signals CA11, CA21, the switch circuit 101 is controlled by a control signal CL. In such a way, the read-out operation extending from the sense amplifier of the initial stage to the sense amplifier of the final stage can be executed by dividing it timewise, and the read-out operation can be executed by the data rate of a higher speed than that of a conventional semiconductor storage device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a plurality of cascade-connected sense amplifiers as a data read circuit section.

[Prior Art] A conventional semiconductor memory device having a plurality of sense amplifiers connected in cascade as a data readout circuit section [Problems to be Solved by the Invention] In these conventional semiconductor memory devices, the first stage is Read operations must be performed continuously from the sense amplifier to the final stage sense amplifier. In other words, the first stage sense amplifier output reaches the final stage sense amplifier,
These sense amplifiers must maintain read operation until output from the output buffer. For this reason, in a semiconductor memory device that is particularly large in scale and has a large number of words, and uses multiple stages of sense amplifiers, it takes a long time for the input of the first stage sense amplifier to reach the final stage. This increases the waiting time for reading the next signal, which is a problem when increasing the operating speed (data rate) of the semiconductor memory device.

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a plurality of cascade-connected sense amplifiers as a data read circuit section, in which a switch circuit is provided between the cascade-connected sense amplifiers. It is characterized by having an interposition.

That is, as shown in FIG. 1 showing a configuration example of the present invention,
A switch circuit 10 is provided between the first stage sense amplifier 111 that senses the read data signal from the memory cell and the last stage sense amplifier 121 that drives the output buffer 141.
1 and sense amplifier control signals CAII and CA21.
The switch circuit 101 is controlled by a control signal C based on the relationship.

[Operation] By interposing a switch circuit at the cascade connection point of cascade-connected sense amplifiers, the operation timing of the sense amplifier in the front stage and the sense amplifier in the rear stage of the switch circuit can be halved.
The read operation can be performed by vibrating operation with a shift of one cycle or one cycle. Therefore, the read operation from the first-stage sense amplifier to the last-stage sense amplifier can be performed in temporally divided manner, making it possible to perform the read operation at a higher data rate than in conventional semiconductor memory devices.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a block diagram of a first embodiment of the present invention. Read data signal DRI from memory cell.

■πDing, DR2, Trπ2. DR3, s*go...
The first stage sense amplifier 211.2 senses each
12,213. ... and the final stage sense amplifier 221 that drives the output buffer 241, and the switch circuit 201 is connected to P-type MoS transistors 251, 252 and N-type MOS transistors 253, 2.
54. First stage sense amplifier 211
, 212, 213, . . . is the control signal CA.
II.

CAl2. CA13. When performing a read operation selected by ..., the switch circuit 201 is made conductive by the control signals CL and TEN (inverted signal of CL).
The output of the first stage sense amplifier is sent to the next stage sense amplifier 221.
0 input section. At the next timing, the operation of the first stage sense amplifier is stopped, and at the same time, the control signal cL, '? f
The switch circuit 201 is cut off by f, and the control signal CA
21 operates the sense amplifier 221, sends a signal to the output buffer 241, and outputs an output signal Do. At this time, the input of the sense amplifier 221 is held by the gate capacitance of the MOS transistor, the diffusion capacitance, and the wiring capacitance, and there is no problem in the operation of the sense amplifier 221 even if it is disconnected from the first stage sense amplifier by the switch circuit 201. Does not occur. At the next timing, the first-stage sense amplifier is operated again, the switch circuit 201 is turned on, and the next data is read, and the same operation as described above is repeated to read the data.

In this embodiment, once the reading by the sense amplifier in the first stage is completed and the data is passed to the input side of the sense amplifier in the next stage, the address for the next read can be changed, etc. Therefore, the cycle time during the read operation can be shortened and the operation speed (data rate) can be improved.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

A switch circuit 30 having a configuration in which capacitive elements 361 and 362 are newly added to the switch circuit 201 of the embodiment shown in FIG.
1 is used. Note that the other configurations are the same as those of the first embodiment, so the same reference numerals are given and redundant explanations will be omitted. By adding the capacitive elements 361 and 362 in this way, the switch circuit 301 (0MO5) transistors 251 to 25
4 is in a cut-off state, the signal can be easily held at the input section of the sense amplifier 2210, and reading can be performed without causing malfunction even at low speed operation. Note that the other operations are the same as in the first embodiment described above.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

This is a case where word division is performed using three stages of sense amplifiers in this embodiment, and the first stage sense amplifiers 411, 412 .
A switch circuit 401 is provided between φ... and the intermediate stage sense amplifier 421, and the intermediate stage sense amplifier 421,
422. A switch circuit 402 is provided between the sense amplifier 431 and the last stage sense amplifier 431. Each switch circuit 401 402 is a P-type MO5) transistor 451, 45
2゜455.456, N type MO5) transistor 453゜454.457, 458, control signal C
Due to L and ■, the switch circuits 401 and 402 operate in opposite phases. In such a configuration, the sense amplifier in the first stage and the sense amplifier in the final stage are operated in the same phase, and the sense amplifier in the intermediate stage is operated in opposite phase.

In addition, when the first stage sense amplifier is operating, the switch circuit 40
1 is in a conductive state, and the switch circuit 402 is in a conductive state while the intermediate stage sense amplifier is operating.

As a result, when the output signal DO is being output, the next read data has reached the input of the intermediate stage sense amplifier 4210, and once the output signal Do has been read,
Furthermore, it is possible to change the address for the next read. In other words, reading can be performed one after another by pipeline operation, so even when word division is performed in multiple stages, the data rate can be shortened and high-speed operation can be performed.

FIG. 5 is a block diagram showing a fourth embodiment of the present invention.

This embodiment is an embodiment in which all stages of the sense amplifiers are operated in the same phase. That is, in this embodiment, the sense amplifiers 511, 512, 513, . . . in the first stage and the sense amplifier 521 in the next stage are operated in the same phase. A switch circuit 52 is provided between the first stage sense amplifier and the next stage sense amplifier.
1 is provided, and a control signal CL is provided so that the switch circuit 501 is in a cut-off state when the sense amplifier is operating and is in a conductive state when the sense amplifier is stopped.

Controlled by three guns. According to such a configuration, when the first-stage sense amplifier operates, charges are accumulated in the capacitive elements 561 and 562 of the switch circuit 501. Then, the operation of the first-stage sense amplifier is stopped, and the control signals CL and τ are used to control the P-type MO5) transistors 551, 552, and the N-type MO8 transistors.
) transistors 553 and 554 turn on and switch circuit 5
01 becomes conductive, the charges in the capacitors 561 and 562 move to the capacitors 563 and 564, respectively, and even if the switch circuit 501 is cut off, the sense amplifier 521
The signal is held in the 0 input section and output to the output buffer 541 without any problem. Here, capacitive elements 561, 56
If the capacitance of the capacitors 563 and 564 is set to about twice that of the capacitors 563 and 564, the potential of the input of the sense amplifier 521 can be easily inverted. Also, N type MO5) transistor 55
5 and 556 are added in order to prevent the potential difference from becoming difficult to invert when the input potential difference of the sense amplifier 521 becomes larger than necessary and the next read data is inverted.

With these, while the sense amplifier is not operating, the switch circuit 501 can transfer data and set the address of the next data to be read, so even when all stages of sense amplifiers are operated in the same phase, pipeline operation can be performed.
High data rates can be achieved.

[Effects of the Invention] As explained above, the present invention provides a semiconductor memory device having a plurality of cascaded sense amplifiers as a data read circuit section, in which one or more of the cascaded sense amplifiers are cascaded. Since the switch circuits are connected in a subordinate manner to the switch circuits, the read operation can be performed in a pipeline operation by shifting the operation timings of the sense amplifier at the front stage and the sense amplifier at the rear stage of the switch circuit by 172 cycles or 1 cycle. As a result, the read operation from the first-stage sense amplifier to the last-stage sense amplifier can be performed in a temporally divided manner, and the read operation can be performed at a higher data rate than a conventional semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example for explaining the invention in detail, FIG. 2 is a block diagram of the first embodiment of the invention, FIG. 3 is a block diagram of the second embodiment of the invention, and FIG. 5 is a block diagram of a third embodiment of the present invention, FIG. 5 is a block diagram of a fourth embodiment of the present invention, and FIG. 6 is a block diagram of a fourth embodiment of the present invention. FIG. 7 is a block diagram of each conventional example. 101, 201. 301゜401.402,501...switch circuit, 141
, 241. 441゜541.641,741...output buffer, 251
, 252. 451゜452.455, 456゜551.552...P type MO5) transistor, 25
3, 254. 453. 454°457, 458
．． 553. 554゜555.556・War・N type M
O5) Ransistor, 111°212°411°422°512°611°712°731 ・121°213°412°431°513°621°721°211°221°421°511°52 1゜711゜722゜... ...Sense amplifier, 381, 362. 561゜562.563,564...Capacitive element, DR, Tn
, DR1°dπ1. DR2, Tf″U:E. DR3, “f5”-π■... Read data signal, Do... Output signal, CAII, CA12. CA13°CA21.
CA22. CA31゜CL, m・・・・・・・・・
····Control signal. Originating data my number DRDR

Claims (1)

[Claims] 1. A semiconductor memory device having a plurality of cascade-connected sense amplifiers as a data read circuit section, characterized in that a switch circuit is interposed between the cascade-connected sense amplifiers.