SU1509890A1 - Arrangement for forming structured files - Google Patents

Abstract

The invention relates to computing and can be used in multiprocessor computing systems for communicating processors with external or storage devices in parallel data processing, as well as information retrieval systems. The device contains two groups of elements AND, element OR, two elements AND, two delay elements, a trigger and a clock pulse generator, an element OR NOT, a decoder, a counter, a group of nodes of the input file, each of which includes two groups of registers, a group of elements And, an element OR, a group of blocks of elements And, a group of comparison circuits. The purpose of the invention is to expand the field of application of the device due to the formation of sets of files ordered according to a given algorithm. The device provides the formation of files of a given structure from the initial array of operands with various features. The order in which file entries are placed for each user is determined by an ordered list of the attributes of these records. The placement of records is performed by successively comparing the features of the operands of the original array with the required ordered lists of signs of the file records for each user simultaneously with the subsequent transfer of the input operands to the corresponding registers of the output file's nodes. Upon completion of the arrangement of records, the device generates a signal that allows users to read files. 1 hp f-ly, 1 ill.

Description

The invention relates to computing and can be used in multiprocessor computing systems for communicating processors with external or storage devices in parallel data processing, as well as in information retrieval systems.

The aim of the invention is to expand the scope by forming file sets arranged according to a predetermined algorithm.

The drawing shows a block diagram of the device.

The device contains registers of 1 group, blocks of elements And 2, blocks of elements of IZ, nodes 4 analysis of the output file, each of which contains registers 5, a group of elements And 6,

a group of comparison circuits 7, the outputs of which are connected to the inputs of the element OR 8, the group of blocks of elements AND 9, registers 10, decoder 11, counter 12, element AND 13, generator of 14 pulses, trigger 15, elements 16 and 17 of delay, element 18, the OR 19 element and the OR-NOT element 20. The device has 21 operand inputs, signal output 22, start input 23, operand number 24 inputs and outputs 25. Consider the principle of construction and operation of the device.

The initial state of the device is characterized by the fact that the counter. 12, trigger 15, registers 5 and 10 are set in the state O (not shown),

The inputs 21 to the corresponding registers 1 receive operands with indicative parts, and the inputs 24 into registers 5 receive ordered lists of numbers of the required types of operands for each consumer.

With the help of, nodes 4 in accordance with the required order of placement of records. The file in output registers 10 is normalized so that the order of arrangement of these records reflects the sequence of accepted signs of operands (records) in register 5. Arrangement of records is made on the basis of alternate comparison of types of operands registers 1 with signs of the required entries placed in registers 5,

Let the initial array of operands, whose attributes are the numbers of the natural number, be received in registers 1. According to these signs, the operands in registers 1 are placed in the following order: 1, 3, 4, 2.

Suppose that for the first consumer it is required to form a file, the records in which are placed in the following order: 1, 2, 3, 4, for the second consumer - 4, 3, 2, 1, and for the third one only one record with sign 4 is necessary.

For this example, in the register 5 of node 4 is taken an ordered list of signs of records: 1, 2, 3,

node 4,

node 4,

-4, 3, 2, 1,

-4, Oh, Oh, 0.

to register

to register j .. j

The operation of the device after placing the necessary information in registers 1 and 5 of nodes 4 begins on a trigger signal received at the input

ten

20

x, e 25

23 and setting the trigger 15 to a single state. A single signal from the direct input of the trigger 15 opens element I 13 and a generator unit binary code is generated by a generator pulse 14 in counter 12. Upon completion of the transients, the counter 12 at the first output of the decoder 11 sets a single signal that opens the AND 2f and And 3 elements. At the same time, binary code 1 from register 1. Through elements 3 is transmitted to the second inputs of circuits 7. With a comparison of all nodes 4. At the same time, the information on the first record from register 1 through elements 2 enters the information inputs of all blocks of elements 9 of nodes 4.

In node 4, a single signal is generated by circuit 7 4. - circuit 7, all circuits 7

 comparison, in node 4 comparison. At node 4j, comparisons form zero signals.

After some time, determined by the delay element 16 and equal to the transient time in the counter 12, the decoder 11 and the AND 2 elements (from) by the delayed generator pulse 14, the record from the register 1 is received at the node 4 into the register 10, through the open block elements And 9, a single signal from the output circuit

7, spawn, in the node

104 through block of elements And 9, in the register

 four

Indoor single signal from the output of the comparison circuit 7. At the same time, through the open signals in a similar way, elements AND 6., in node 4 and elements AND 64 in node 4 are set to zero state, respectively, registers 5 and 5.

The delayed additionally by the delay element 17 of the generator pulse 14 does not affect the state of the trigger 15, since at the output of the iinil element 19 a zero signal is held which closes the element 18.

The second generator pulse 14 in the counter 12 generates the binary code of the number 2 and, similarly to the information considered, from the register Ij affects the circuit elements so that in node 4 a record is taken in register 10, the sign of which is 2, and register 5 is set to zero . In node 4. in the South register this entry is accepted, and

register 5y is set to zero.

Similarly, the third pulse generator generator operand (recording from register 1 is transmitted in node A, in register 10, in node -s register 10, and in node 4, in register 10, in addition, in node 4 the register 5 is suppressed, node 4, - register 5, in node 4 - register 5 |.

On the fourth pulse, the transmission of the operand (record) from the register C in node 4 to register 10, in node 4, to register 10, with simultaneous damping of register 5 in node 4 and register 5 in node 4, is also ensured in the same way.

At the end of the recording of information on the fourth pulse of the generator 1, a single signal is present at the fourth output of the decoder 11, and at the output of the OR-NOT element 20, since all the registers 5 of the nodes 4 are set to zero, a single signal is generated. In this case, AND 18 is opened by a single signal from the output of the element | OR 19, and by a delayed pulse of the generator 14, the delay element 17 is set to the zero state trigger 15 The output 22 is set to a single signal, which allows the transfer of information organized in files from the outputs 25 user m. In this case, from the registers 10 of the node 4 records in the file are placed in the established order of signs: 1, 2, -3, 4, from the registers 10 of the node 4, 3, 2, 1, from 1 zogr 10 node 4, - 4, Oh, Oh, 0.

For other tasks of placing records in files, the operation of the device does not differ from that described.

Completion of the device to form the structure task files is performed after viewing all records of registers 1 or after placing records in registers of 10 nodes 4.

In the first case, the trigger 15 is extinguished by a single signal from the output of the decoder 11, and in the second, by a single signal from the output of the OR-NOT 20 element after setting 5 registers to the zero state 4. If necessary, use the device in the next cycle condition.

Claims (2)

1. A device for generating structured files containing a group of registers, two groups 0 AND elements, trigger, clock generator, two AND elements, two delay elements, OR element and group of input file analysis nodes, the device operand input groups are connected to the group of information inputs of the group registers, the first group of outputs of each group register is connected to the group information inputs of the same block 0 AND elements of the first group, the elevations of which are combined and connected to the first group of information inputs of the analysis nodes of the group input file, the output of the clock pulse generator 5 is connected to the first input of the first element I, the second input of which is connected to the forward output of the trigger, the zero output of which is signal output device 0 the start input of which is connected to a single trigger input, the reset input of which is connected to the output of the second element I, the first input of which is connected to the output of the first delay element, the clock outputs of the nodes of the analysis of the group input file are connected via the second delay element to the B code of the first element I , the second groups of information inputs of the analysis nodes of the second file of the group are connected to the input groups of the device operand numbers, the group of outputs of the nodes, the analysis of the input file of the group are the output groups of the device, different In order to expand the field of application by forming file sets arranged according to a given algorithm, a decoder, a counter and an IL11-HE element are inserted into the device, the counter input of the counter is connected to the output of the first And element and the second the delay element, the output of which is connected to the input of the first delay element; the signal outputs of the analysis nodes of the input file of the group are connected to the inputs of the element OR; NOT, the output of which is connected to the first 0 five 0 the input of the OR element, the second input and output of which are connected respectively to the last output of the decoder and to the second input of the second element AND, the third group of information inputs of the analysis nodes of the group input file is connected to the outputs of the AND blocks of the second group, the inputs of the decoder are connected to the counter outputs , each output of the decoder is connected to the control input of the block of the same name of the elements of the first and second groups, the second group of outputs of each register of the group is connected to the group of information inputs of the same name Lok elements and the second group. 2. The device according to claim 1, which means that each node analyzing the input file of a group contains two groups of registers, a group of comparison circuits, an OR element, a group of AND elements, a group of AND blocks of elements, whose output groups are connected to groups of information inputs of the same register of the first n 5 0 five groups whose outputs are groups of outputs of a node whose clock input is connected to the first control inputs of the blocks of elements AND of the group, the second control input of each block of elements AND of the group is connected to the output of the same name comparison circuit of the group, the first group of inputs Each comparison circuit of the group is connected to the group of outputs of the second group of the same name register, the second groups of inputs of the comparison circuits of the group are connected to the third group of information inputs of the node, the outputs of the registers of the second group are connected to the inputs of the OR element, the output of which is the signal output of the Wela, the first inputs of the AND elements of the group are connected to the clock input of the node, the second input of each element of the AND group is connected to the output of the group comparison circuit of the same name, the output of each AND element of the group is connected to the reset input of the same name register of the second group, group of information inputs blocks of elements And groups are connected to the first group of information inputs of the node.