SU1732347A1 - Test data generator - Google Patents

Abstract

This invention relates to the field of computing. The purpose of the invention is to increase the completeness of the generated test. The generator contains a synchronization node 1, an address flow generator 2, a memory node 3, a node 4 periodically correcting the cells, a start input 5, outputs 6. The set of generated test actions is greater than the set of node 3. The test is guaranteed correct. Test actions are generated with the frequency of operation of the node 3. 2 Cp. Of the file, 6 Il.

Description

9 X

eight

/ J

6

ten

15

12

/,

sixteen

 WITH

Yu

Sl)

five

17,

18

11 and

four

to. /

The invention relates to the field of computer technology and can be used in high-speed testers designed to test digital nodes such as circuit boards and microchips.

The purpose of the invention is to increase the completeness of the generated test by increasing the set of generated test actions and chains of test actions.

FIG. 1 shows a structural diagram of the generator; in fig. 2 - functional synchronization node diagram; in fig. 3 is a functional diagram of an address stream maker; in fig. 4 - the memory node is functional; in fig. 5 is a functional diagram of a node for periodic cell correction; in fig. 6 - a functional diagram of the generator N pulses.

The test generator (Fig. 1) contains a synchronization node 1, an address stream generator 2, a memory node 3 and a cell 4 regular correction node 4 and has a start input 5 and outputs 6. The input 5 is connected to the start input 7 of node 1. The outputs 8 of node 1 connected to inputs 9 - 1-1 synchronization of driver 2, node 3 and node 4, respectively. Outputs 6 are connected to outputs 12 of node 3. Outputs 13 of generator 2 are connected to inputs 14 of the reading address of node 3. Record address inputs 15 and informational inputs 16 of the node 3 are connected respectively with the first 17 and second 18 outputs of the node 4.

Node 1 synchronization (Fig. 2) contains the generator 19 N pulses, the delay element 20, the one-shot 21, the counter 22.

Shaper 2 of the address stream (FIG. 3) contains a counter 23, a memory block 24 and a register 25.

Memory node 3 contains (Fig. 4) the first 26 and second 27 multiplexers, the first 28 and second 29 memory blocks, the first 30 and second 31 elements OR NOT, the element 32 and the register 33.

The node 4 of the periodic cell correction (Fig. 5) contains a pseudo-random number generator 34, a memory block 35 and a register 36.

The generator 19 N pulses contains (Fig. 6) the generator 37 of the sync series, the counter 38, the element 39 And, the trigger 40 and the element And 41,

The test generator works as follows.

After starting the test generator through the input 5, the driver 2 generates the final stream of addresses. At each address generated by shaper 2, from node 3 reading of the test action on outputs 6 takes place.

To each address b of the node 3, a certain set Tb of permissible values are assigned (from the point of view of correctness

generated test) test effects. After starting the test generator, node 4 from time to time writes a new value to the cell with the address b of node 3, as

which uses a randomly selected test effects set Tb.

Before the first start of the test generator, the contents of the node 3 cells are undefined. Therefore, the first generation of the test is not

0 use. At the end of the first (as well as any subsequent) generation in the cell with the address b of node 3 (for each b), one of the test effects of the set Tb will be found. When repeatedly reading a cell with the ad5 res b of node 3, performed during any test generation, starting from the second, different test effects of the set T b will be read out at output 7. At the same time, a lot of generated test effects

0 will be greater than the set of node cells 3. Consider the operation of the nodes of the test generator.

The synchronization node 1 (Fig. 2 operates as follows. The pulse that starts it, arrives at input 7 through input 5, is short-term O. This O clears generator 19 and counter 22 and is transmitted to output 8.3. At the end of the starting pulse, the generator starts 19, which gives N clock pulses, where N is the number of test actions in the generated test. Each clock pulse switches the counter 22 and through element 20 (providing a delay for the time of the end of transients that are triggered by the test generator Turning off the counter 22) starts the one-shot 21, which forms a gate at the output 8.1. The counter 22 outputs 1 to the output 8.2.

0 in every nth cycle (for the value of n, see below). The shaper 2 address stream (Fig. 3) works as follows. O, arriving at input 9.2, resets counter 23 and register 25. At the end of each gate arriving at input 9.1, counter 23 switches, working with a recalculation coefficient m equal to the number of cells of block 24, Counter 23 sets the address to block 24. Read from block 24, the word is entered in the register

0 25, with the output of which enters the outputs 13, the consecutive cells of the block 24 during its programming must be entered in the corresponding addresses constituting the generated stream of addresses. In order for the addresses to be repeatedly encountered in this stream, they must be written into many cells of block 24. In addition, if N is made much larger than t, then during the test generation the address flow generated by shaper 2 will be repeated cyclically.

The memory node 3 (Fig. 4) operates as follows. Depending on the state X of the most significant bit (input through input 14.2) of the reading address, reading is performed in register 33 (at the address input through inputs 14.1) from block 28 (with X 1) or block 29 (with X 0). If the reading is performed from block 28, then block 29 is available for writing (at the address coming through inputs 15) of the test action coming through inputs 16. Otherwise, the roles of blocks 28 and 29 are reversed,

Node 4 of the periodic cell correction (Fig. 5) works as follows, O, entering input 11.3, resets generator 34 and register 36. At the end of the gate entering input 11.1, generator 34 and register 36 are switched, but only in this case if input 11.2 arrives at 1. Last arrives at every nth cycle, where n is the number of ticks during which a read operation from block 35 occurs. The generator 34 generates a pseudo-random address for block 35. The word read from block 35 is entered into register 36 and it contains the Address field coming in 17 s, and the field effect Test supplied to the outputs 18. Address field contains the address of a node b 3, and the field effect Test - one of the plurality of test stimuli Tb.

The generator 19 N pulses (Fig. 6) works as follows. The generator 37 generates a continuous sync series. If trigger 40 is in state 1, then it passes through element 41 to generator 19, and also causes counter 38 to switch. Trigger 40 is set to O through element 39 by applying O through generator R’s input 19, or by the counter transfer output signal 38. The counter 38 and the trigger 40 at the end of the sync pulse generated by the generator 37 are reset to 0 if 1 is fed to the input C of the generator 19.

Claims (3)

Claim 1. A test generator comprising an address stream driver and a memory node, the outputs of the memory node are generator outputs, the inputs of the memory node reading address are connected to the outputs of the address stream generator, in order to increase the completeness of the generated test , the node of the periodic cell correction and the synchronization node are entered into it, where the inputs of the address of the memory node record are connected to the first outputs of the node of the periodic cell correction, the information inputs of the memory node are connected to the second outputs The node of the periodic cell correction node, the synchronization trigger start input is connected to the generator start input, the first synchronization node output is connected to the first synchronization inputs of the address flow generator, the memory node and the periodic cell correction node, the second synchronization node output is connected to the second synchronization inputs of the memory node and a node of the periodic cell correction, the third output of the synchronization unit is connected to the third synchronization inputs of the address flow generator and the node of the periodic cell correction. 2. Generator pop. 1, distinguishing 5 with the fact that the node periodic correction the cells contain a pseudo-random number generator, a memory block and a register, with the outputs of the pseudo-random number generator connected to the address inputs of the memory block, 0 whose outputs are connected to the information inputs of the register, the first and second outputs of which are connected respectively to the first and second outputs of the node, the synchronization inputs of the pseudo-5 random number generator and the register are connected to the first synchronization input of the node, the enable switches of the pseudo-random number generator and the register are connected to the second input node synchronization 0 reset inputs of the pseudo-random number generator and the register are connected to the third synchronization input of the node, 3. The generator of PP, 1 and 2, characterized in that the memory node contains two 5 multiplexers, two memory blocks, two OR-NOT elements, a NOT element and a register, the first information inputs of the multiplexers are connected to the input addresses of the node record, the second information ones. 0 multiplexer inputs are connected to the I / O addresses of the node, excluding the last hour of the node's read address, which is connected to the address input of the first multiplexer, the read enable input of the first block 5 memory, the first input of the first element OR NOT and the input of the element NOT, the output of which is connected to the address input of the second multiplexer, the read enable input of the second memory block and the first input 0 of the second element OR NOT, the outputs of the memory blocks are connected to the information inputs of the register, the outputs of which are the outputs of the node, the address inputs of the first memory block are connected to the outputs of the first multiplexer, the address inputs of the second memory block are connected to the outputs of the second multiplexer, information the inputs of the memory blocks are connected to the information inputs of the node, the inputs for enabling the selection of memory blocks and the synchronization input the register is connected to the first input of the sync-OR-NOT connected to the second synchronization input of the node, the second inputs of the node's internalization elements. (Reg. 2 Fy K 8.1 K8.2 / (83 FIG. five J7 ER 38 Nb R 41 Js h 40 FIG. 6