JPS6363215A - Chattering removal device - Google Patents

Abstract

PURPOSE:To surely remove both a level H noise overlapping with the level L of an input signal and a level L noise overlapping with a level H by setting or resetting a 1st latch circuit according to the input signal and the logic of an output signal from a 2nd latch circuit. CONSTITUTION:When both the input signal (b) and the output signal (d) are at level H, a setting gate 6(AND circuit) setting the latch circuit 3 is provided. When the input signal (b) changes from H to L level and a clock signal (a) falls during a level L session, the output signal (c) of the latch circuit 3 also changes to level L. If the input signal (b) is returned to level H before a next clock fall point, both the input signal (b) and the output signal (d) go down to level H, and the latch circuit 3 is set through the setting gate 6(the signal (c) is at level H). Even if the input signal (b) includes the level H noise with width smaller than that of one clock and if the noise coincides with the clock fall point, the noise is not transmitted to the output signal (d).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a chattering removal device that removes and shapes the chattering and noise of a logic signal generated by turning on/off a switch, for example.

One typical configuration of a conventional chattering removal device is disclosed in Japanese Patent Application Laid-open No. 5
It is disclosed in Japanese Patent No. 9-16419.

The configuration and operation of this conventional device are shown in FIGS. 3 and 4.

In Fig. 3, 1 and 2 are a switch and a pull-up resistor as input signal sources, which generate an input signal that is H level when switch 1 is off and L level when it is on, and is input to the chattering removal device. be done.

The input signal A is latched by the first latch circuit 3 (D-type flip-flop) in synchronization with the falling point of a predetermined clock signal a. The output signal C of this first latch circuit 3 is
It is latched by the second latch circuit 4 (D-type flip-flop) in synchronization with the rising point of the same clock signal a. 1 after the output signal C of the first latch circuit 3 changes.
The output signal d of the second latch circuit 4 changes with a delay of the clock. This signal d becomes the output signal after chattering has been removed.

Reference numeral 5 denotes a reset gate (NOR circuit) for forcibly resetting the first latch circuit 3, which resets the first latch circuit 3 when both the input signal and the output signal d become L level. Set output signal C to L level.

As shown in FIG. 4, even if the input signal becomes H level for a short period of time, if the fall of the clock signal a does not coincide with the falling point of the clock signal a during that H level period, the first latch circuit 3. It is not transmitted to the second latch circuit 4 (see noise Nl, chattering C1). A change in the L level of the input signal a will not be transmitted to the subsequent stage unless it coincides with the falling point of the clock signal a (see chattering C2).

As shown by the noise N2, the input signal A remains at the H level for a short period of time (less than one clock), and when the clock signal a falls during this H level period, the output signal C of the first latch circuit 3 becomes H level. Change in level. However, if the input signal becomes L level before the next clock falling point, both the input signal S and the output signal d become L level, and the first latch circuit 3 is reset through the gate 5. In other words, the noise N2 is not transmitted to the output signal d.

The problem that the invention seeks to solve The conventional device shown in FIG. 3 had the following problems.

As shown by noise N3 in FIG. 4, suppose that while the input signal is continuously at the H level, the input signal becomes the L level for a short time due to some noise. This L
When the clock signal a falls during the level period, the output signal C of the first latch circuit 3 changes to L level. This change is transmitted to the second latch circuit 4 at the next falling edge of the clock, and the output signal d also changes to L level. In other words, the noise N3 is expanded to a width of one clock and appears in the output signal d.

The present invention was made in view of the above-mentioned conventional problems, and an object thereof is to provide a chattering removal device that can reliably remove both H level noise and L level noise of an input signal.

Means for Solving the Problems Therefore, in the present invention, in a configuration in which a first latch means and a second latch means synchronized with a predetermined clock signal are connected in series to transmit an input signal to an output, the input signal and the second latch means are connected in series. a reset gate for resetting the first latch means when the output signal of the two latch means becomes one logic state; A setting gate for setting the latch means is provided.

Even if the action input signal changes to H level and the output signal of the first latch means changes to H level, if the input signal returns to L level before the output signal of the second latch means changes to H level, The first latch means is reset through the reset gate.

Furthermore, even if the input signal changes to L level and the output signal of the first latch means changes to L level, if the input signal returns to H level before the output signal of the second latch means changes to L level. , the first latch means is set through the cent gate.

Embodiment The structure and operation of an embodiment of the chattering removal device according to the present invention are shown in FIGS. 1 and 2.

In FIG. 1, a switch 1 and a pull-up resistor 2 as input signal sources, a first latch circuit 3 that latches an input signal in synchronization with a falling edge of clock signal a at 9, and a first latch circuit 3 that latches an input signal in synchronization with falling edge of clock signal a The first latch circuit 3 is synchronized with
The second latch circuit 4 that latches the output signal C of
It has the same configuration as the conventional device shown in the figure, and its operation is also the same.

In addition to the above-mentioned configuration, the device of the present invention shown in FIG. It has been established.

In the waveform diagram of FIG. 2, noises Nl and N2 and chattering CI and C2 are removed by the same effect as described above.

As shown by noise N3, the input signal changes from H level to L level.
When the lock signal a falls during the L level period, the output signal C of the first latch circuit 3 also changes to the L level. However, if the input signal returns to H level before the next clock falling point, both the input signal and output signal d become KH level, and the first latch circuit 3 is set through the setting gate 6. (Signal C becomes Hv level). Therefore, even if the input signal contains L level noise with a short width of one clock or less and coincides with the falling point of the clock, that noise will not be transmitted to the output signal d.

Effects of the Invention As explained in detail above, in this invention, two systems of gates are provided to set or reset the first latch circuit according to the logic of the input signal and the output signal of the second latch circuit. , it is possible to reliably remove both the H level noise superimposed on the L level of the input signal and the L level noise superimposed on the H level.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a chattering removal device according to an embodiment of the present invention, FIG. 2 is a timing chart showing its operation, FIG. 3 is a configuration diagram of a conventional chattering removal device, and FIG.
The figure is a timing chart showing the operation of the conventional device. 3.--First latch circuit, 4... Second latch circuit, 5
...Reset gate, 6...Set gate, a
...clock signal, b...input signal, d...output signal.

Claims (1)

[Claims] a first latch means that latches an input signal in synchronization with a predetermined clock signal; a second latch means that latches an output signal of the first latch means in synchronization with the same clock signal; a reset gate that resets the first latch means when the output signal becomes one logic state; and a reset gate that sets the first latch means when the input signal and the output signal of the second latch means become the other logic state. A chattering removal device equipped with a set gate.