JPS60148218A - Signal processing device - Google Patents

Abstract

PURPOSE:To output a signal of a prescribed pulse width in synchronizing with an input signal without being affected by chattering of the input signal by giving respectively an output signal of one coincident gate on one hand and to a reset terminal of the other RSFF circuit on the other hand. CONSTITUTION:An output terminal of an NAND gate 4 is connected to a reset terminal 15a of the RSFF circuit 15 comprising NAND gates 13, 14 and an output terminal 15b of the circuit 15 is connected to a signal output terminal 6. Moreover, an output terminal 11b of the RSFF circuit 11 is connected to a reset terminal 15c of the circuit 15 and an output terminal 15d of the circuit 15 is connected to a reset terminal of FF circuits 8, 9. Thus, an output signal of prescribed pulse width in synchronizing with the leading edge of the input signal is obtained by latching the output of the gate 4 at the circuit 15 so as to prevent the effect of chattering from appearing in the output signal even if the input signal carries chattering.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides a method for synchronizing the leading edge of an input signal to -
This invention relates to a signal processing device that generates a pulse signal longer than the indicated time, and is effective when used to shape the waveform of a frequency generator (FG) output pulse in a capstan drive motor circuit of a video tape recorder, etc. .

Configuration of a conventional example and its problems Hereinafter, a conventional signal processing device will be described with reference to the drawings. FIG. 1 is a circuit configuration diagram of a conventional signal processing device, in which 1 is a signal input terminal to which an input signal whose level changes at an arbitrary time is applied, and WAND gates 2 and 1 (
A set terminal 11 of an RS flip-flop circuit 11 constituted by an AND gate 3 is connected to the set terminal 11 of the RS flip-flop circuit 11 . 4 has the output terminal 11b of the 1879717191 circuit 11 as the first input terminal, and the signal input terminal 1 as the second input terminal.
5 is the NAND gate connected to the NA
This is an inverter that inverts the output of the ND gate 4, and its output terminal is connected to the signal output terminal 6. 7 is an input terminal to which a clock pulse is applied. Reference numerals 8 and 9 denote flip-flops having a reset function, each of which has its reset terminal connected to the output terminal of the NAND gate 4. A clock signal input terminal of the flip-flop 8 is connected to an input terminal 7 to which a clock pulse is applied. A clock signal input terminal of the flip-flop 9 is connected to the inverted output Q of the flip-flop 8. 1o is an Nm ND gate in which the non-inverting output terminals of flip-flops 8 and 9 are connected to the input terminal. The output terminal of the HAND gate 1Q is connected to the reset terminal 11C of the 1879717191 circuit 11. A delay pulse generation circuit 12 is composed of a flip-flop 8.9 and a NAND gate 10.

Regarding the conventional signal processing device configured as described above,
Its operation will be explained below. Figure 2 shows the signal waveforms of each part of the circuit in Figure 1.
) are respectively clock signal input terminal 7° signal input terminal 1
This is the signal waveform applied to. Also, Fig. 2(c) +
(a) + (e) + (fl + (cy) +
(hl l (i) is a NAND game respectively)2,
3,4. Flip-flop 8.9, NAND gate 10
．． This is the output signal waveform of the ear bar 15.

Time t. When the level of the signal input terminal 1 shifts from "o" to "1", the output level of the NAND gate 4 shifts from "1" to "0", and the reset of the flip-flops 8 and 9 is released. Further, the output of the inverter 5 is an inversion of the output signal of the NARD gate 4, and its output level shifts from o'' to 1''. After the reset of the flip-flops 8 and 9 is released, at time t1, when the level of the clock pulse input terminal 7 changes from 0'' to 1'', the level of the non-inverted output of the flip-flop 8 also changes from 0'' to 1''. 1".

At time t4, when the level of the clock pulse input terminal 7 shifts from 0' to 11' again, the level of the non-inverted output of the flip-flop 8 shifts from 1" to #0", thereby causing the non-inverted output of the flip-flop 9 to shift from 1" to #0". The level of the inverted output shifts from #o# to 1'.

At time t5, when the level of the clock pulse input terminal 7 shifts from 0" to 1', the level of the non-inverted output of the flip-flop 8 shifts from '0.' to .1', and the N A N, D gate 1o output level from 1' to 0
” and RS free.

The flop circuit 11 is reset. Said 18797
When the 17191 circuit 11 is reset, the output level of the WAND gate 4 changes from 0' to 1'', and as the flip-flops 8 and 9 are reset, the output level of the inverter 5 changes from 11'' to o''. .

When the flip-flops 8 and 9 are reset, N
The output level of the A tV D gate 10 shifts from 01 to 1#, and the series of operations ends.

At time t6, when the level of the signal input terminal 1 changes from 1' to 0'', the RS flip-flop 11 is set and enters a standby state for the next series of operations.

At time t7, when the level of the signal input terminal 1 changes from 0'' to 1'', the output level of the ND gate 4 changes from 0'' to 1''. '1# to 0. After that, the output level of each gate changes in the same way as from time t to t5.

Now, a signal waveform as shown in FIG. 2 (il) appears at the output terminal of the inverter 5, that is, the signal output terminal 6 in FIG. It can be seen that an output signal with a pulse width can be obtained.

However, in the above configuration, for example, the third
As shown in the figure, if the signal waveform applied to the signal input terminal 1 shifts from 1" to 0" at time t2 and shifts from ○' to 11" at time t3, and chattering occurs, at time t2 Since the output level of the NAND gate 4 shifts from 0# to 1'', the level of the output signal shifts from #1'' to #o#, the flip-flops 8 and 9 are reset, and the signal processing circuit is on standby. Then, at time t3, when the signal waveform applied to the signal input terminal 1 shifts from 0'' to 1'', the output level of the NA)iD gate 4 shifts from 〃1g to 〃o. , the output level of each gate changes in the same way as from time t1 to time t5 shown in FIG.

Therefore, when chattering occurs in the input signal, a similar chattering phenomenon also appears in the output signal, causing malfunctions such as when measuring frequency.

OBJECTS OF THE INVENTION An object of the present invention is to provide a signal processing device that outputs a signal with a constant pulse width synchronized with the leading edge of an input signal without being affected by chattering or the like in the input signal. It is.

Structure of the Invention The signal processing device of the present invention includes a first R879717671 circuit to which an input signal is applied to a set terminal, and a first coincidence gate to which the input signal and the output signal of the first R879717671 circuit are applied to input terminals. and a 20th gate whose set terminal is supplied with the output signal of the first coincidence gate.
an RS flip-flop circuit and the second RS flip-flop circuit.

The output of the first . This configuration includes a delay pulse generation circuit that is applied to at least one reset terminal of the second RS flip-flow knob circuit, so that even if chattering occurs in the input signal, the input signal is not affected by the input signal. It outputs a signal with a constant pulse width that is synchronized with the signal.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 shows a circuit configuration diagram of a signal processing device according to an embodiment of the present invention. Components that are the same as those in FIG. 1 are given the same reference numerals, and redundant explanations will be omitted. The following points differ between FIG. 1 and FIG. 4. The output terminal of the NARD gate 4 is connected to the set terminal 151L of the second RS flip-flop circuit 15 constituted by the HAND gate 13 and the HAND gate 14, and the output terminal 16b of the second RS flip-flop circuit 16 is used for signal output. Connected to terminal 6. The tip terminal 11b of the first RS flip-flop circuit 11 is connected to the reset terminal 15C of the second RS flip-flop circuit 16. The output terminal 15 (i) of the second RS flip-flop circuit 15 is connected to the reset terminals of flip-flop circuits 8 and 9 having a reset function.

The operation of the signal processing device of this embodiment configured as described above will be described below. Figure 6 shows the signal waveforms of each part of the circuit in Figure 4.
b) are signal waveforms applied to the clock input terminal 7 and the signal input terminal 1, respectively.

Also, Fig. 6 (c) + (ti) + (e) +
(fl l ((1) I (hl l (i) l
(:ll is NANI respectively) Gates 2, 3, 4, 13
, 14, the output signal waveforms of the flip-flop circuits 8, 9, and the NARD gate 10.

Time t. The level of signal input terminal 1 changes from 0'' to 1
'', the output level of NAND gate 4 becomes ``1''.
to 10#, the second RS flip-flop circuit 15 is set, and its output 15 b Iti O'' changes to 1'', and the level of the signal output terminal 6 also changes from o'' to 1.
The second RS flip-flop circuit 1
5's output terminal 15 (1 transitions from 1'' to 0'', and the reset of the flip-flop circuits 8 and 9 is released.

At time t1, when the level of the clock pulse input terminal 7 changes from 0'' to 1'', the level of the non-inverted output of the above-mentioned )'Jy flipflop circuit 8 changes from 0# to 1''.

At time t4, when the level of the clock pulse input terminal 7 changes from 0'' to 1'', the level of the non-inverted output of the flip-flop circuit 8 changes from 1'' to 0'',
This makes it free.

The level of the non-inverted output of the flip-flop circuit 9 ranges from 0' to 11.
”.

At time t5, when the level of the clock pulse input terminal 7 changes from 0'' to 1'', the level of the non-inverted output of the flip-flop circuit 8 changes from 0' to 1'',
As a result, the HAND game) 10(7) output level is 5.
The signal changes from 1' to 0', and the first RS flip-flop circuit 11 is reset. When the first RS flip-flop circuit 11 is reset, its output terminal 11b
The level of . . . changes from . . . 1 to . . 0. The output level of the HAND gate 4 changes from . When the RS flip-flop circuit 16 is reset, the level of its output terminal 15b, that is, the signal output terminal 6 shifts from 1'' to 0''.
Since the level of the other output terminal 16d of the RS flip circuit 16 shifts from 0'' to 1', the RS flip,
Pfronop circuits 8 and 9 are reset, the output level of )IAND gate 1o shifts from 0# to 1'', and the series of operations ends.

At time t6, when the level of the signal input terminal 10 changes from 1' to 0'', the first RS flip-flop circuit 11 is set and enters a standby state for the next series of operations.

At time t7, when the level of the signal input terminal 1 shifts from o'' to 1'' since the output level of the N A li D gate 2 has been set to 1'' in advance, HAND
The output level of the gate 4 shifts from #1'' to o'', and thereafter the output level of each gate changes in the same way as from time t1 to +5.

Now, a signal waveform as shown in FIG. 5(f) appears at the output terminal 15b of the second RS flip-flop circuit in FIG. It can be seen that an output signal with a constant pulse width synchronized with the leading edge can be obtained.

FIG. 6 shows signal waveforms at various parts when the input signal causes chattering. When the signal waveform applied to the signal input terminal 1 changes from 11' to 0'' at time t2, the output level of the NAND gate 4 changes from 0'' to 1.
”.

However, the second +7. The RS flip-flop circuit 16 is activated at time t. Since it has not been reset after being set, the output level of the second RS flip 70 tube circuit 16 does not change. Therefore, the flip-flop circuits 8 and 9 are not reset either.

Then, at time t3, the level of the signal input terminal becomes 0' again.
When the output level shifts from #1' to 1'', the output level of the NAND gate 4 shifts from #1' to 10'', returning to the state before chattering occurred. The waveform of the output level of the valley gate after time t4 is the same as the waveform of the output level after time t4 in FIG.

Therefore, even when chattering occurs in the input signal, the waveform at the output signal terminal is the same as when no chattering occurs in the input signal.

As described above, according to this example, by latching the output of the NAND gate 4 with the 1'RS flip-flop circuit 15, even if the input signal chattering occurs, the effect will not appear on the output signal. An output signal with a constant pulse width synchronized with the leading edge of the input signal can be obtained.

Note that the present invention is not necessarily limited to the configuration shown in FIG. 4, and the combination of NAND gates can be replaced with other matching gates such as NOR gates.

Effects of the Invention As is clear from the above description, the present invention includes a first RS flip-flop circuit to which an input signal is applied to a set terminal, and a connection between the input signal and the output of the first RS flip-flop circuit to the input terminal. a first coincidence gate to which a signal is applied, a second RS flip-flop circuit to which an output signal of the first coincidence gate is applied to a set terminal, and an output of the second RS flip-flop circuit to a reset terminal. a clock pulse is applied to the clock signal input terminal, and an output signal is output from the first . second 18797170
Since the configuration includes a delayed pulse generation circuit applied to at least one reset terminal of the 71 circuit, even if input signal chattering occurs, it will not be affected by it and will generate a constant pulse width synchronized with the input signal. The excellent effect of being able to output a signal is obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a conventional signal processing device, FIGS. 2 and 3 are signal waveform diagrams of each part of FIG. 1, and FIG. 4 is a circuit configuration diagram of a signal processing device according to an embodiment of the present invention. 5 and 6 are signal waveform diagrams of each part in FIG. 4. 1. Signal input terminal, 2, 3, 4, 10, 1
3゜14...NAND gate, 5...Inverter, 6...Signal output terminal, 7...Clock pulse input terminal, 8, 9...Furi, Grofflog Circuit, 11.15・・RS flip, flop circuit, 1
2...Delayed pulse generation circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3 Figure 401

Claims (3)

[Claims] (1) a first RS logic circuit whose set terminal receives an input signal; a first coincidence gate whose input terminal receives the input signal and the output signal of the first RS7S7 logic circuit; and a center terminal. a second RS flip-flop circuit to which an output signal of the first coincidence gate is applied; an output of the second RS flip-flop circuit is applied to a reset terminal; a clock pulse is applied to a clock signal input terminal; and the output signal is the first one. A signal processing device comprising a delay pulse generation circuit applied to at least one reset terminal of a second R879717071 circuit. (2) The delay pulse generation circuit is connected to a flip-flop having a first reset function in which a clock pulse is applied to a clock signal input terminal, an output of the second RS flip-flop is applied to a reset terminal, and the second RS flip-flop has a clock signal input terminal. The output of the flip-flop having a first reset function is connected to a second flip-flop having a reset function, whose reset terminal is given the output of the second RSS free lag flop; Flip 70 with a reset function. 2. The signal processing device according to claim 1, wherein the signal processing device is constructed using a second matching gate to which an output of the second matching gate is applied. (3) The output signal of the second coincidence gate is given to the reset terminal of the first RS flip-flop circuit, and the output signal of the first coincidence gate is given to the reset terminal of the second RS flip-flop circuit. A signal processing device according to claim (2), characterized in that: