JPH02174417A - D flip-flop circuit - Google Patents

Abstract

PURPOSE:To test in a short time without consecutive application of clocks by controlling D FP transfer gates in tandem connection with a prescribed signal formed from a clock and a test signal at the test. CONSTITUTION:A clock 10 and a test signal 9 via an inverter 11 are processed by a NAND gate 12, signals CNB 16, CPB 18 controlling a D FF gate 1 of a master section 5 are generated similarly by NOR processing and signals CP 17, CN 10 controlling a D FF gate 3 of a slave section 6 by the clock 10 and the signal 9 are generated. Then a P-channel gate 1 and an N-channel gate are closed thereby conducting the test of D FF gates in tandem connection of the master-slave system not by a consecutive clock but by a single clock quickly.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit, and in particular to a CMOS D-type flip-flop circuit using a master-slave system. The flip-flop circuit includes a master part consisting of a first transfer gate that is turned on by an inverted clock signal and a first inverter connected to the output of the first transfer gate, and a master part that is made up of a first transfer gate that is turned on by an inverted clock signal and a first inverter connected to the output of the first transfer gate. A slave device consisting of a second transfer gate connected to the output of the first inverter and turned on by a normal clock signal, and a second inverter connected to the output of the second transfer gate. At the rising edge of the clock signal, the master part latches the data signal that is input to the first transfer gate, and sends out that signal to the slave part, while at the rising edge of the clock signal, the master part latches the data signal that is input to the first transfer gate. The data signal sent from the master part is sent to the outside, and the signal is latched at the falling edge of the clock signal.

[Problem to be solved by the invention]

The conventional D-type flip-flop circuit described above cannot send a data signal unless the lock signal is activated, so when these D-type flip-flop circuits are connected in tandem, the data signal is output to the outside during testing. In order to do this, the clock signal must be input many times, which is time-consuming.

An object of the present invention is to provide a D-type flip-flop circuit that solves the above problems.

[Means to solve the problem]

To achieve the above object, the present invention provides a master-slave type CMO5 D-type flip-flop circuit in which an inverted test signal and a clock signal are connected to the gate of an N-channel transistor constituting a transfer gate that is made conductive by an inverted clock signal. Connect the NANDed signal, connect the inverted clock signal and the NORed signal of the test signal to the gate of the P-channel transistor,
Furthermore, a clock signal is connected to the gate of an N-channel transistor constituting a transfer gate that is rendered conductive by a clock signal, and an inverted signal of the clock signal is connected to the gate of a P-channel transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. In FIG. 1, transfer gates 1 and 3 are composed of a combination of a P-channel transistor and an N-channel transistor. The input of the transfer gate l is connected to the data signal 7, and the gate inputs of the N-channel transistor and the P-channel transistor are respectively connected to the inverted signal of the test signal 9 and the output of the NAND of the clock signal CNB 16, and the inverted output of the clock signal 10 and the test signal. NOR output C of signal 9
It is connected to PB18. Transfer gate 1
The master part 5 of this D-type flip-flop circuit is constituted by the inverter 2 connected to this output.

On the other hand, the slave section 6 is composed of a transfer gate 3 and an inverter 4 connected thereto, and the input of the transfer gate 3 is connected to the output of the inverter 2 which is the output of the master section 5.

The gate input of the N-channel transistor of the transfer gate 3 is connected to the same signal CN15 as the clock signal 10, and the gate input of the P-channel transistor is connected to the CP multiplied signal (clock inverted signal) 17 obtained by inverting the clock signal lO by the inverter 13. There is.

When the test signal is LOld, the D-type flip-flop circuit of the present invention described above performs the same operation as the conventional D-type flip-flop circuit, and the master part 5 latches the data signal 7 at the rising edge of the clock signal 10. , and transfers the data to the slave section 6 at the next rising edge of the clock signal 10.

On the other hand, the slave section 6 outputs the output of the master section 5 to the output 8, and latches it at the rising edge of the clock signal.

Next, when setting the test mode by setting the test signal 9 to )light, if the clock signal 10 is set to
Signal 15. The CNB signal 16 becomes High and cp
Signal 17. Since the CPB signal (clock inversion signal) 18 is both LOW, transfer gates 1 and 3
becomes conductive, and the data signal 7 is sent as is to the data output 8.

〔Effect of the invention〕

As explained above, the present invention allows a clock signal to be input as a high-level signal to the gate of the N-channel transistor of the transfer gate, and not to the gate of the P-channel transistor during the test so as not to latch the data signal in the test mode. By changing the circuit to apply a 0Ill level signal, the gates between D-type flip-flops can be tested without operating the clock signal during testing, which has the effect of shortening test time. be.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a D-type flip-flop of the present invention. 1.3... Transfer gate 2.4, 11.13... Inverter 5... Master part 6... Slave part 7... Data signal 8... D type flip-flop output 9...・Test signal 10...Clock signal 12...NAND 14...N
0R17...Clock inversion signal

Claims (1)

[Claims] (1) In a master-slave type CMOS D-type flip-flop circuit, the inverted test signal and the N-channel transistor that constitutes the transfer gate are connected to the inverted test signal and the clock signal.
Connect the ANDed signal and connect the inverted clock signal and the NO test signal to the gate of the P-channel transistor.
A clock signal is connected to the gate of the N-channel transistor constituting the transfer gate which is made conductive by the clock signal, and an inverted signal of the clock signal is connected to the gate of the P-channel transistor. A D-type flip-flop circuit.