JPH04220810A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To prevent the flip-flop circuit of a CMOS logic integrated circuit from being in the meta-stable state. CONSTITUTION:An exclusive OR gate 11 receives an output signal of a transfer gate 1 receiving a data signal for a master latch and an input signal of a transfer gate 2 inputting the latched data to the master latch. An OR gate 19 gives an output of the exclusive OR gate 11 added to a clock signal to the transfer gates 1,2 of the master latch. An inverter 10 being a clock signal supply logic inverting gate inverts an output logic of the OR gate 19 and gives the result to transfer gates 3,4 of a slave latch.

Description

[Detailed description of the invention]

0001

FIELD OF INDUSTRIAL APPLICATION The present invention is applied to a flip-flop circuit of a CMOS type logic integrated circuit. In particular, the present invention relates to a metastable prevention circuit for flip-flop circuits.

0002

2. Description of the Related Art A conventional flip-flop circuit, as shown in FIG. 1, and inverters 29 and 10 that sequentially apply latching signals to the transfer gates. When the latching signal at point B is "H", the data signal at point A passes through transfer gate 1 and inverter 5 and 6.
is held by the master latch. Next, when the levels at points C and D become equal, the latching signal at point B becomes "L", transfer gate 1 is closed and transfer gate 2 is opened, and the data is latched. At the same time, transfer gate 3 opens and the inverted data is input to the slave latch. This is further inverted via inverter 7 and output to point G, and the data is held in a slave latch by inverters 7 and 8. Next, B becomes "H" again, transfer gate 3 closes and transfer gate 4 opens, the data becomes stable in the slave latch, and on the master latch side, transfer gate 1 opens and data from the outside is input again. Perform a series of movements.

0003

[Problem to be Solved by the Invention] In such a conventional flip-flop circuit, when the data input signal from point A changes when sampling data with the master latch, the latching occurs before the changed data reaches point D. The signal changes from "H" to "L", and the transfer gate 2 opens while the level difference between point C and point D remains, which has the disadvantage of causing metastability.

The present invention solves these drawbacks and provides a flip-flop circuit that can prevent metastability by transmitting a latching signal to a transfer gate after the levels at points C and D become equal. The purpose is to

[0005]

[Means for Solving the Problems] The present invention provides a flip-flop circuit equipped with a master latch and a slave latch each composed of a transfer gate and a logic inverting gate, on the output side of the transfer gate that inputs a data signal to the master latch. An exclusive OR gate whose inputs are the signal and the signal on the input side of the transfer gate which inputs the latched data signal to this master latch, and an output obtained by adding the output of this exclusive OR gate to the clock signal is added to the master latch. The present invention is characterized in that it includes an OR gate for supplying a clock signal to the transfer gate of the slave latch, and a logic inverting gate for supplying a clock signal by inverting the output logic of the OR gate and supplying the inverted output logic to the transfer gate of the slave latch.

[0006] Here, the flip-flop circuit may be composed of a transfer gate and a NAND gate.

[0007]

[Operation] The latter transfer gate is opened after the output side signal level of the transfer gate inputting the data signal to the master latch becomes equal to the level of the input side signal of the transfer gate inputting the latched data signal to the master latch. This prevents the flip-flop circuit from entering a metastable state.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment, and FIG. 2 is a timing chart explaining its operation.

As shown in FIG. 1, this embodiment employs a master-slave system consisting of a master latch made up of transfer gates 1 and 2 and inverters 5 and 6, and a slave latch made up of transfer gates 3 and 4 and inverters 7 and 8. a flip-flop circuit, and an exclusive OR gate 1 whose inputs are a signal on the output side of transfer gate 1 and a signal on the input side of transfer gate 2.
1, a metastable prevention circuit consisting of an OR gate 19 that adds the output of the exclusive OR gate 11 to a clock signal, and an inverter 10 that provides an inverted clock signal to the transfer gate. Also point A
A data input signal is provided at point B, and a clock input signal is provided at point B.

That is, in this embodiment, as shown in FIG. 1, in a flip-flop circuit equipped with a master latch and a slave latch, each of which is composed of a transfer gate and a logic inverting gate, a transfer gate inputs a data signal to the master latch. 1 and the input side signal of transfer gate 2 which inputs the data signal latched to this master latch, and the output of this exclusive OR gate 11 is clocked. OR gate 1 that provides the output added to the signal to transfer gates 1 and 2 of the master latch.
9, and an inverter 10 which is a logic inverting gate for supplying a clock signal by inverting the output logic of the OR gate 19 and applying it to the transfer gates 3 and 4 of the slave latch.

Further, as shown in FIG. 3, the flip-flop circuit is composed of a transfer gate and a NAND gate.

Next, the operation of this embodiment will be explained using FIG. 2.

Initially, "L" data is input at point A, but when it changes to "H", at point C it changes from "L" to "H", but at point D, the "L" data is still input. Even if point B changes from "H" to "L", point E remains unchanged for time a.
Since it is "H", the output point F of the OR gate 19 remains "H" without transmitting the change from "H" to "L" at point B. When the level at point C and the level at point D become equal at "H", point E changes from "H" to "L", and point F changes from "H" to "L". In this way, the transfer gate 2 opens only when the levels at points C and D become equal and stable, thereby preventing metastability and making it possible to stabilize the sampling state in the master latch. Furthermore, it is clear that a similar effect can be obtained with a set/reset flip-flop circuit in which inverters 5, 6, 7, and 8 are replaced with NAND gates.

[0014]

Effects of the Invention As explained above, the present invention provides a signal on the output side of the transfer gate that inputs the data signal to the master latch, and a signal on the input side of the transfer gate that inputs the latched data signal to the master latch. Since it is equipped with an exclusive OR gate that adds the output of this exclusive OR gate to a clock signal, it has the effect of preventing the appearance of a metastable state in which the data latch state becomes unstable. be.

[Brief explanation of the drawing]

FIG. 1 is a circuit connection diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart explaining the operation of the embodiment of the present invention.

FIG. 3 is a circuit connection diagram showing the configuration of a second embodiment of the present invention.

FIG. 4 is a circuit connection diagram showing the configuration of a conventional example.

[Explanation of symbols]

1, 2, 3, 4 Transfer gate 5, 6, 7, 8
, 10, 29 Inverter 11 Exclusive OR gate 19 OR gate

Claims (2)

[Claims] Claim 1: In a flip-flop circuit equipped with a master latch and a slave latch configured with a transfer gate and a logic inversion gate, a signal on the output side of the transfer gate that inputs a data signal to the master latch and a signal latched to the master latch are provided. An exclusive OR gate whose input is the signal on the input side of the transfer gate that inputs the data signal, and an OR gate which supplies the output of the exclusive OR gate added to the clock signal to the transfer gate of the master latch. and a logic inversion gate for supplying a clock signal, which inverts the output logic of the OR gate and supplies the inverted output logic to the transfer gate of the slave latch. 2. In a flip-flop circuit equipped with a master latch and a slave latch configured with a transfer gate and a NAND gate, a signal on the output side of the transfer gate inputting a data signal to the master latch and a signal latched to the master latch are provided. an exclusive OR gate whose input is a signal on the input side of a transfer gate that inputs a data signal, and an OR gate which adds the output of this exclusive OR gate to a clock signal and supplies the output to the transfer gate of the master latch. 1. A flip-flop circuit comprising: a gate; and a logic inverting gate for supplying a clock signal for inverting the output logic of the OR gate and applying the inverted output logic to the transfer gate of the slave latch.