JPH0483414A - Latch circuit - Google Patents

Abstract

PURPOSE:To obtain a latch circuit shortening a signal propagation time and appropriate for high integration by providing the latch circuit with the 4th transmission means for positively or inversely rotating the inversion logical level of the 1st control signal and outputting the rotated result. CONSTITUTION:In the case of selecting the positive rotation logical level or inverted rotation logical level of a data input signal l, a transmission gate 5 or a clocked inverter 4 is alternatively turned to a conductive state. Since a timing signal 7 is turned to '0', transmission gates 3, 5 are turned to non- conductive states and the clocked inverters 4, 6 are turned to conductive states so as to form a positive feedback loop for holding the state of a data output signal 2. Consequently, the propagration delay time can be shortened, a circuit speed can be accelerated, circuit size and a wiring area can be reduced and the latch circuit appropriate for high integration can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a latch circuit having a function of normal inverting or inverting the logic level of a data input signal.

[Conventional technology]

When performing addition and subtraction in a digital arithmetic circuit, a function is required to normalize or invert the logic level of the data input signal and latch it. Conventionally, circuit configurations shown in FIGS. 3 and 4 are well known as latch circuits used for such applications.

The latch circuit shown in FIG.
It consists of an exclusive NOR circuit 104 for normal rotation or inversion operation. In the circuit configuration shown in FIG. 3, when the selection signal 103 is "0", the data input signal 101
The inverted logic level of ``1'' is latched, and the selection signal 103 becomes ``1''.
'', the normal logic level of the data input signal 101 is latched. Furthermore, in the latch circuit having the circuit configuration shown in FIG.
By selectively controlling the conduction of the clocked inverter 113 or the transmission gate 114 using the negative phase signal 120, the normal or inverted logic level of the data input signal 111 is latched. In the circuit configuration shown in FIG. 4, when the clocked inverter 113 is controlled to be conductive, the normal logic level of the data input signal 111 is changed to the inverted logic level of the data input signal 111, and when the transmission gate 114 is controlled to be conductive, the inverted logic level of the data input signal 111 is set to the inverted logic level of the data input signal 111. 115 as the output signal 112. FIG. 5 shows the configuration of a control circuit that generates the control signals 117 and 119 shown in FIG.
3 and the timing signal 121, when the timing signal is "1", the clocked inverter 1 of FIG.
Control signals 119 and 120 for controlling the conduction of the clocked inverter 113 or control signals 117 and 118 for controlling the conduction of the transmission gate 114 are alternatively output, and when the timing signal 121 is "0", the clocked inverter 113 Transmission gate 114 and transmission gate 114 are both controlled to be non-conductive, and are brought into a latched state by clocked inverter 116 which is controlled to be conductive by timing signal 121.

[Problem to be solved by the invention]

However, in the conventional technology as described above, in the case of the circuit configuration shown in FIG. 3, the exclusive NOR circuit 104 is interposed in the signal propagation path, so not only is the propagation delay time for the signal output large, but also the digital operation When used as a circuit register, an exclusive NOR circuit is required for each bit, resulting in an increase in circuit scale.

Although the circuit configuration shown in FIG. 4 does not have the above-mentioned problems, it requires a control signal output as shown in FIG. When used in this case, at least four control signals are required for the latch circuit shown in FIG. 4, including an anti-phase signal, which increases the ineffective wiring area and is not suitable for high integration.

Therefore, the present invention is intended to solve these problems, and its purpose is to provide a latch circuit that has a short signal propagation time until an output signal is obtained and is suitable for high integration. .

[Means to solve the problem]

The latch circuit of the present invention includes a data input terminal, and a first transmission means that is connected to the data input terminal and outputs the result by normal rotation or inversion of the logic level of the data input terminal based on the logic level of a first control signal. a second transmitting means for inverting the logic level of the first transmitting means with the logic level of a second control signal and outputting the inverted logic level of the second transmitting means; third transmitting means for outputting an output logic level at an inverted logic level of the second control signal;
a fourth transmitting means for outputting the output by normalizing or inverting the output logic level of the outputs of the second and third transmitting means connected in common with the inverted logic level of the first control signal; The output of the fourth transmission means is commonly connected to the output of the first transmission means.

〔Example〕

Hereinafter, the present invention will be explained in detail based on the embodiments shown in FIGS. 1 and 2.

FIG. 1 shows a latch circuit showing one embodiment of the present invention. ]
2 is a data input signal, 2 is a data output signal, 3 is a first transmission means constituted by a transmission gate whose conduction is controlled by a timing signal 7 (reverse phase signal 8), and 4 is a first transmission means configured by a control signal 9 (reverse phase signal 10). 5 is a second transmission means composed of a clocked inverter whose conduction is controlled; 5 is a third transmission means composed of a transmission gate whose conduction is controlled by a control signal 10 (reverse phase signal 9); 6 is a timing signal 8 (reverse phase signal 9); This is the fourth transmission means composed of a clocked inverter whose conduction is controlled by the phase signal 7).

The operation of the circuit shown in FIG. 1 will be explained. The transmission gate 3 becomes conductive when the timing signal 7 is "1" and transmits the data input signal 1 to the inputs of the second and third transmission means. At the same time, when the normal logic level of the pig input signal 1 is selected, the transmission gate 5 is selectively turned on, and when the inverted logic level of the data input signal 1 is selected, the clocked inverter 4 is selectively turned on. Become. Then, when the timing signal 7 becomes "O", the transmission gates 3 and 7 become non-conductive,
When clocked inverters 4 and 6 become conductive, a positive feedback loop that maintains the state of data output signal 2 is formed.

By the way, the control signal 9 (reverse phase signal 10
) is generated as shown in Table 1 from the timing signal 7 and a selection signal for selecting normal rotation or inversion operation of the latch circuit.

Table 1 As is clear from Table 1, either the clocked inverter 4 or the transmission gate 5 only needs to be in a conductive state for all manual states, and the control that generates the control signals 9 and 10 is sufficient. The circuit can be constructed of a NAND circuit 12 of the timing signal 7 and the selection signal 11 as shown in FIG. Two pieces are enough.

〔Effect of the invention〕

As described above, according to the present invention, the third
Unlike the circuit configuration shown in the figure, an exclusive NOR circuit is not required on the signal propagation path, so the propagation delay time can be shortened as in the case of the circuit configuration shown in FIG. 4, and the speed of the circuit can be increased. Furthermore, in the present invention, the control signal of the latch circuit can be generated using a simple circuit as shown in FIG. 2, and the number of control signals is as small as 2, so the circuit scale and wiring area can be reduced. This has the effect of being suitable for high integration.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a latch circuit showing an embodiment of the present invention, FIG. 2 is a circuit configuration diagram of a control circuit that controls the operation of the latch circuit shown in FIG. 1, and FIGS. 3 and 4 are conventional circuit diagrams. FIG. 5 is a circuit diagram of a control circuit for controlling the operation of the latch circuit of FIG. 4; 1...Data input signal 2...Data output signal 3.5...Transmission gate 4.6...Clocked inverter 7...Timing signal 8...7 Negative phase signal 9... Control signal 10... Negative phase signal 11 of 9... Selection signal 12... NAND circuit 13... Inverter 101... ...Data manual signal 102...Data output signal 103...Selection signal 104...Exclusive NOR circuit 105.107
- Clocked inverter 106... Inverter 108... Timing signal 109... Reverse phase signal 110 of 108... Latch circuit 111... Data input signal 112... ...Data output signal 113, 116, clocked inverter 114...
・Transmission gate 115...Inverter 117.119 ・Control signal 118.120・Reverse phase signal 121 of 117.119...
... Timing signal 122 ... 121 opposite phase signal 123 ... Selection signal 124 ... NOR circuit 125.126.128 - ... Inverter 127 ... - NAND circuit and above Applicant Seiko Epson Co., Ltd. agent Patent attorney Kizobe Suzuki (and 1 other person) No.

Claims (1)

[Scope of Claims] A data input terminal, and a first transmission means connected to the data input terminal and configured to output a result of normal rotation or inversion of the logic level of the data input terminal based on the logic level of a first control signal. , a second transmission means that inverts the logic level of the first transmission means with the logic level of a second control signal and outputs the result; and a second transmission means that is connected in parallel with the second transmission means and outputs the inverted logic level of the first transmission means. a third transmission means for outputting a logic level at an inverted logic level of the second control signal; and a third transmission means for controlling the output logic level of the outputs of the second and third transmission means connected in common to the first control signal. and a fourth transmitting means that outputs a signal by normal rotation or inversion at an inverted logic level, and the output of the fourth transmitting means is commonly connected to the output of the first transmitting means. latch circuit.