KR950008460B1 - Detector out of input condition - Google Patents

Abstract

The proposed no-input state detection circuit, which is relatively simple to implement, consumes less power than the conventionalshift-register and, detects the existence of data from the input. The circuit includes: (a) a bit clock(CK) which is used to read the serial data(I); (b) a no-input state detector(11) which detects the no-input situation when the subframe starting signal(EN) is activated; (c) a counter which sets the system signal high when the no-input state continues for a set time.

Description

Inputless state detection circuit

1 is a block diagram showing a conventional no-input state detection circuit.

FIG. 2 is a detailed circuit diagram of the inputless detector of FIG.

3 is a block diagram showing an input state detection circuit according to the present invention.

4 is a detailed circuit diagram of the no-input detector of FIG.

5A to 5H are timing charts for FIGS. 3 and 4 when serial data is input.

6A-6I are timing diagrams for FIGS. 3 and 4 when no serial data is input.

* Explanation of symbols for main parts of the drawings

11: no input state detector 12: counter

IV1, IV2: Inverter A1, A2: NAND gate

TN1: Transmission Gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inputless state detection circuit of a digital audio interface (hereinafter referred to as DAI) IC, and more particularly, to an inputless state detection circuit for reducing power consumption by detecting an inputless state using a simplified circuit. .

The non-input state detection circuit used in the conventional DAI IC includes a 32-bit shift register 10 for converting serial data into parallel data when serial data is input, as shown in FIG. A non-input state detector 20 for detecting a no-input state by parallel data output from the 32-bit shift register 10 and a counter 30 for controlling the system in the case where an input-in state is detected for a predetermined time or more. It is composed.

Referring to the operation according to the configuration, first, when the serial data is loaded into the 32-bit shift register 10 and converted into parallel data, the non-input state detector 20 shown in FIG. 2 detects the presence or absence of data. .

If no input continues for a certain period of time using the counter 30 to give a certain time margin, it is regarded that data is not input and the ciscon signal is set to 'high logic level'. To stop the operation of the system. If data is input while the counter 30 is operating, the counter 30 The system will continue to operate.

However, since the conventional inputless state detection circuit described above is implemented using random logic, there is a problem in that the number of logic gates configuring the inputless state detector and the 32-bit shift register is large.

Accordingly, an object of the present invention is to provide a no-input state detection circuit that can implement a circuit as well as reduce the power consumption by detecting the presence of data input to the system by introducing a feedback concept to solve the above problems. .

In order to achieve the above object, the present invention provides a non-input state detector for detecting a non-input state of data, and counts a counter clock for a predetermined time by detecting a non-input state of data in the non-input state detector. A non-input state detection circuit having a counter for detecting whether an input-free state of data persists for a time, the input-free state detector comprising: a first inverter for inverting input data; A first NAND gate for performing NAND logic on the output signal of the first inverter and the output signal of the transfer gate; A second NAND gate for performing NAND logic on a signal indicating that a subframe is started and an output signal of the first NAND gate and applying the output signal to the counter: a second for inverting a bit clock reading the data inverter ; And an output signal of the second NAND gate is applied to an input terminal, an output signal of the second inverter is applied to a first control terminal, and the bit clock is applied to a second control terminal so that the first control terminal and the second control terminal are applied. And a transmission gate for transmitting an output signal of the second NAND gate to an input terminal of the first NAND gate according to a logic of a signal applied to a control terminal.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a block diagram showing a no-input state detection circuit according to the present invention.

The non-input state detecting circuit shown in FIG. As a result of detection by the no-input detector 11 and the no-input detector 11 for detecting a no-input state from the system, it is assumed that no data is inputted to the system. Cone signal to 'high logic level' It consists of a counter 12 for making.

4 is a detailed circuit diagram of the non-input state detector 11 in FIG.

The non-input state detector 11 shown in FIG. 3 includes a first inverter IV1 for inverting the serial data I, an output signal W1 of the first inverter IV1, and a transfer gate TN1. A first NAND gate A1 for performing NAND logic on the output signal W3 of the signal, a signal EN indicating that a sub-frame starts, and an output signal W2 of the first NAND gate A1. The second NAND gate A2 for applying the output signal to the counter 12, and the second inverter IV2 for inverting the bit clock CK for reading the serial data I. ), An output signal of the second NAND gate A2 is applied to the input terminal, an output signal CKB of the second inverter IV2 is applied to the first control terminal, and serial data I is applied to the second control terminal. It consists of a transfer gate TN1 to which a bit clock CK for reading is applied.

5a to 5h are timing charts for FIGS. 3 and 4 when serial data is input, FIG. 5a is a ciscon signal, FIG. 5b is a signal EN indicating that a sub-frame is started, 5c is a bit clock CK for reading serial data I, 5d is serial data I, 5e is an output signal W1 of the first inverter IV1, and 5f is a first NAND gate ( The output signal W2 of A1, FIG. 5g is the output signal W3 of the transmission gate TN1, and FIG. 5h is the output signal O of the non-input state detector 11, that is, the output of the second NAND gate A2. Each signal O is shown.

6a to 6i are timing charts for FIGS. 3 and 4 when no serial data is input, FIG. 6a is a scissor signal, FIG. 6b is a clock signal CC of the counter 12, and FIG. 6C is a subframe ( A signal EN indicating the start of the sub-frame, FIG. 6d is a bit clock CK for reading the serial data I, FIG. 6e is the serial data I, and FIG. 6f is the first inverter INV1. Output signal W1, FIG. 6g is an output signal W2 of the first NAND gate A1, FIG. 6h is an output signal W3 of the transfer gate TN1, and FIG. 6i is an output signal of the no-input detector 11 (O), that is, the output signal O of the second NAND gate A2, respectively.

Next, the operation of the present invention will be described with reference to FIGS. 3 to 6.

The case where data is input to the no-input state detection circuit according to the present invention will be described with reference to FIGS. 3 to 5, and the case where no data is inputted is shown in FIGS. The description is as follows.

First, when data is input to the system ('high' logic level section in FIG. 5d), in the no-input state detector 11, the first inverter IV1 inverts the serial data I (FIG. 5d). Outputs the low logic level as the output signal W1 (Fig. 5e), and the first NAND gate A1 is connected to the output signal W1 (Fig. 5e) of the first inverter IV1 and the transfer gate TN1. As a result of performing the NAND logic on the output signal W3 (Fig. 5G), the logic level 'high' is output as the output signal W2 (Fig. 5F). The second NAND gate A2 performs NAND logic on the output signal of the first NAND gate A1 (figure 5f) and the signal EN (figure 5b) indicating that the sub-frame starts. As a result, the logic level 'low' is output as the output signal O (Fig. 5h).

The counter 12 receives a signal of the 'low' logic level (FIG. 5h) output from the no-input detector 11. Terminals( Is accepted by the counter 12 Therefore, the sciscon signal, which is the output signal of the counter 12, maintains the 'low' logic level.

On the other hand, when no data is input to the system (the 'low' logic level section in Fig. 6e), in the no-input state detector 11, the first inverter IV1 receives the serial data I (Fig. 6e). Inverts to output a 'high' logic level as the output signal W1 (Fig. 6f), and the first NAND gate A1 is the output signal W1 (Fig. 6f) of the first inverter IV1 and the transfer gate TN1. As a result of performing the NAND logic on the output signal W3 (Fig. 6h), the output signal W2 (Fig. 6g) outputs a 'low' logic level. The second NAND gate A2 performs NAND logic on the output signal W2 (FIG. 6g) of the first NAND gate A1 and the signal EN (FIG. 6c) indicating that the sub-frame starts. As a result, the logic level 'high' is output as the output signal O (Fig. 6i).

The counter 12 receives the signal of the "high" logic level (Fig. 6i) output from the no-input detector 11. By accepting it to the terminal R, Therefore, the counter 12 counts the clock signal CC (Fig. 6B) for a predetermined time. In this case, when the count is performed for a predetermined time, the ciscon signal, which is an output signal of the counter 12, becomes a 'high' logic level. Control by turning off the system power. On the other hand, when data is input again within a predetermined time, the sciscon signal, which is the output signal of the counter 12, becomes a 'low' logic level, so that the sciscon signal has no effect on the system.

As described above, in the inputless state detection circuit according to the present invention, the inputless state detector, which is a component thereof, is configured by using two inverters, two NAND gates, and a transfer gate to remove 32-bit shift registers. This not only simplifies the circuit but also reduces the power consumption.

Claims (1)

A non-input state detector for detecting a non-input state of data and a no-input state of data in the non-input state detector, the counter clock is counted for a predetermined time so that the non-input state of the data is maintained for the predetermined time. A no-input state detection circuit having a counter for detecting whether or not a first input is detected, said no-input state detector comprising: a first inverter for inverting input data; A first NAND gate for performing NAND logic on the output signal of the first inverter and the output signal of the transfer gate; A second NAND gate configured to perform NAND logic on a signal indicating the start of a subframe and an output signal of the first NAND gate and apply the output signal to the counter; A second inverter for inverting a bit clock reading the data; And an output signal of the second NAND gate is applied to an input terminal, an output signal of the second inverter is applied to a first control terminal, and the bit clock is applied to a second control terminal so that the first control terminal and the second control terminal are applied. And a transmission gate for transmitting an output signal of the second NAND gate to an input terminal of the first NAND gate according to a logic of a signal applied to a control terminal.