JPS594316A - Data latch circuit - Google Patents

Abstract

PURPOSE:To constitute simply a latch circuit inverting an output in synchronization with an input signal and a clock pulse, by using a circuit element comprising two C-MOS inverters and two MOS transistors(TRs). CONSTITUTION:The 1st C-MOS inverter CL1 inverts an input data signal Di and supplies the output to the 1st MOS TRT1. The 2nd C-MOS inverter CI2 is connected to the output of the 1st MOS TRT1. The 2nd MOS TRT2 given to a clock pulse CLK is connected to the 1st MOS TRT1. Thus, a latch output where either one of the inverted rise and fall is synchronized with the clock pulse and the other is inverted in synchronization with the input data signal, is obtained at an output OUT of the 2nd MOS inverter CI2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data latch circuit using C-MOS, and its purpose is to invert either the rising edge or the falling edge of an output data signal. To provide a data latch circuit with a simple circuit configuration, in which one side changes in synchronization with a zero pulse signal and the other side changes in synchronization with the inversion of an input data signal.

Examples will be described below using figures. FIG. 1 shows an embodiment of the present invention (CIIXCI is C-M
The OS inverter (TtXT*) is a MOS transistor, which inverts the input data signal (D).
The output signal (Ql) of the OS inverter (Ct, ) is passed through the first MOS l- transistor ('r+) to the second MO
A clock pulse signal (Vc p
), and the second C-MOS inverter (
The input signal (Q2) of CI2) is input to the gate of the second MOS transistor (I2), and the input signal (Q2) of
Two MOS l-transistors (TtX
It is sufficient that the TJ is made of the same chisesinel, and the P-MOS
%N-MOS may be used. In the figure (Voo) (■s
s) is the power supply voltage, (IN) is the input terminal, (CLK) i
j: OFF terminal, (otn'') is an output terminal.

Now, Figure 2 shows the MOS transistor (1゛θ(I2)
When using N-MOS as
(a) Beam 0 terminal (CLK)
The clock pulse signal (vCp) input to the same figure (b
) is the input gate signal (■
1), the same figure (C) is MOS) 5:/ji2:51(
TI) gate signal (Vo), the same figure (Φ is the output signal (Qυ) of the C-MOS inverter (CII), the same figure (e) t
The output signal of the iRI0/νri circuit (CL), that is, C-MO
Input signal of S inverter (CRS) (Q, same figure (f)
is the output terminal (OU
This is the output data signal (Q, ) outputted via T). In this case, when the input signal (possible) of the C-MOS inverter (C1*) is at the tXL n level, the transistor (
Since the gate signal (VG) of 'l'l) is fixed at the "H" level, the operation of the C-MOS inverter (CI) is independent of changes in the output pulse signal (Vcp). Therefore, the rising edge of the output data signal (Q,) is inverted in synchronization with the rising edge of the output pulse signal (Vcp), and the falling edge of the output data signal (Q,) is inverted in synchronization with the falling edge of the input data signal (DI). .

Figure 8 shows MOS t' transistor ('I't) (Tg)
This shows a time chart when P-MOS is used as a C-MOS inverter (CI
When the input signal (Q2) of M
The gate signal (VG) of the OS l-transistor (T,) becomes "L" and is fixed at the bell, and the C-MOS
The operation of the inverter (CI) is based on the clock pulse signal (Vc
It becomes unrelated to changes in p). Therefore, the rising edge of the output data signal (Q2) is synchronized with the rising edge of the input data signal (Di), and the falling edge of the output data signal (Q2) is synchronized with the rising edge of the clock pulse signal (Vc
This is done in synchronization with the falling edge of p), and the synchronization relationship is opposite to that in the case of FIG.

As described above, the present invention inputs the output signal of the first C-MOS inverter that inverts the input gator signal to the second C-MOS inverter via the first MO5t-laser resistor, and inverts the first MOS transistor. A clock pulse signal is input to the gate through the second MOS transistor, and the input signal of the 20th C-MOS inverter is input to the second MOS transistor.
This is the input to the gate of the OS l-transistor.
Two data latch circuits are provided in which one of the rising inversion and falling υ inversion of the output data signal changes in synchronization with the clock pulse signal, and the other changes in synchronization with the inversion of the input data signal. C-MOS
It can be formed from an inverter and two MOS transistors, has a simple circuit configuration, and can be applied to various flip 7099 circuits.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram of one embodiment of the present invention! @Figure 2 (a) −
(f) and FIGS. 8(a) to 8(f) are operation explanatory diagrams of the same as above. (CI, XCI,) are C-MOS inverter (T
1), (Tri is a transistor. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

[Claims] (1) The output signal of the 10th C-MOS inverter that inverts the input signal is input to the second C-MOS inverter via the first MOS l-transistor, and
A clock pulse signal is input to the gate of the OS transistor via the second MOS l' transistor, and the input signal of the second C-MOS inverter is input to the second MOS transistor.
A data latch circuit that is input to the gate of a transistor.