JP2000307394A - Clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generating circuit that has provision for a high frequency signal. SOLUTION: This circuit is provided with a NAND circuit 12 whose one input terminal receives an output waveform from an input signal line 11 and whose other input terminal receives an output waveform of a signal line 13 branched from the input signal line 11 via a delay circuit 14 consisting of an odd number of stages of inverters 14A, 14B, 14C, 14D, 14E. The output waveform from this NAND circuit 12 is outputted to an output signal line 16 via an inverter 15, and P-channel MOS transistors(TRs) 17, 18, 19, which receive the changes in the level of the pulse waveform of the inverters 14A, 14C, 14E from a high level into a low level, are connected after the odd number stage inverters 14A, 14C, 14E being the components of the delay circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a technique for providing a clock generation circuit for generating a clock based on a waveform change point.

[0002]

2. Description of the Related Art As shown in an equivalent circuit diagram of FIG. 3, a clock generation circuit for generating a clock based on a change point of a waveform has an input signal line 1 and a signal line 1 connected to one of NAND circuits 2. A signal line 3 branched from the signal line 1 is input to the other end of the NAND circuit 2 via a delay circuit (delay) 4 in which a plurality (odd number) of stages are arranged.
Further, the circuit configuration is such that the output from the NAND circuit 2 is output to the output signal line 6 via the inverter 5.

[0003] Such a clock generation circuit outputs a pulse waveform as shown in FIG.

That is, a low-level / high-level pulse waveform (refer to a pulse waveform (A) shown in FIG. 4) is input to one of the NAND circuits 2 from the input signal line 1, and a signal branched from the signal line 1. A pulse waveform of the opposite level (high level / low level) of the input signal line 1 (see the pulse waveform (B) shown in FIG. 4) output from the line 3 through the odd-numbered delay circuits 4 is the NAND circuit. Enter the other side of 2. Then, the output from the NAND circuit 2 is inverted by the inverter 5 and output to the output signal line 6 (see the pulse waveform (C) shown in FIG. 4).

As described above, the pulse waveform (C) in the clock generation circuit rises when the rising of one pulse waveform (for example, pulse waveform (A)) is detected, and the other pulse waveform (for example, pulse waveform (A)). A) falls when the falling of the delayed pulse waveform (B)) is detected.

[0006]

Here, a problem arises when the clock generation circuit is designed to cope with high frequencies. In this case, when the pulse waveform period of the pulse waveform (A) becomes faster, the reset by the pulse waveform (B) is delayed as shown in FIG. 5 (the rising of the pulse waveform (B) by the dashed line (1) is desired). (Pulse waveform (B) is a pulse waveform indicated by a dotted line in the pulse waveform (B)), and a constant pulse waveform is not always output from the waveform change point.
T1 <T2 (T1 + period delayed compared to the pulse waveform (C) shown by the dotted line)).

Therefore, in the present invention, the pulse waveform (A) is clocked up, and the pulse waveform (C) that follows the clock is increased.
It is an object of the present invention to provide a clock generation circuit capable of outputting a clock signal.

[0008]

Therefore, in the clock generation circuit of the present invention, the output waveform from the input signal line 11 is input to one input terminal, and the input signal line 11 is input to the other input terminal.
A logic circuit (NAN) is supplied with an output waveform from a signal line 13 branched from a delay circuit 14 including odd-numbered stages of inverters 14A, 14B, 14C, 14D, and 14E.
D circuit 12) and an output waveform from the NAND circuit 12 is output to an output signal line 16 via an inverter 15,
Further, following the odd-numbered stage inverters 14A, 14C and 14E constituting the delay circuit 14,
P-channel MOS transistors 17, 18, which reset the signal of the delay circuit portion in response to the change of the pulse waveforms of A, 14C, 14E from high level to low level,
19 is interposed.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a clock generation circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is an equivalent circuit diagram showing an embodiment of the clock generation circuit of the present invention.

In FIG. 1, reference numeral 11 denotes an input signal line. The signal line 11 is inputted to one of NAND circuits 12, and the other of the NAND circuit 12 has a plurality of (odd) signal lines 13 branched from the signal line 11. Delay circuits (delays) 14 arranged in stages (for example, inverters 14A, 14B, 14
C, 14D, and 14E). Also,
The output from the NAND circuit 12 is output to the output signal line 16 via the inverter 15. The circuit configuration so far is the same as the conventional circuit configuration, and various pulse waveforms as shown in FIG. 2 are output. That is, the input signal line 11
A low-level / high-level pulse waveform (see the pulse waveform (A) shown in FIG. 2) is input to one of the NAND circuits 12 and the signal line 13 branched from the signal line 11.
The pulse waveform of the opposite level (high level / low level) of the input signal line 11 (see the pulse waveform (B) shown in FIG. 2), which is output from the Enter the other. And this NAN
The output from the D circuit 12 is inverted by the inverter 15 and output to the output signal line 16 (see the pulse waveform (C) shown in FIG. 2).

As described above, the pulse waveform (C) in the clock generation circuit rises when the rising edge of one pulse waveform (for example, pulse waveform (A)) is detected, and the other pulse waveform (for example, pulse waveform (A)). A) falls when the falling of the delayed pulse waveform (B)) is detected.

The clock generation circuit according to the present invention is characterized in that, after the odd-numbered inverters 14A, 14C, 14E constituting the delay circuit (delay) 14, the pulses of the inverters 14A, 14C, 14E are respectively provided. The configuration is such that the change of the waveform (A) from the high level to the low level is received by the P-channel MOS transistors 17, 18, and 19, and the signal of the delay circuit (delay) 14 is reset.

As a result, the falling period of the pulse waveform (A) of the related art (FIG. 5) is shortened (compared to the dashed line (1) in FIG. 5). (In the pulse waveform (C) of FIG. 2, the rising period T1 and the rising period T2 are equal or almost equal.), The clock of the pulse waveform (A) is increased. Since the pulse waveform (C) following the pulse waveform (C) can be obtained, it is possible to cope with a high frequency. 3), the problem that the constant pulse waveform is not always output from the waveform change point can be solved.

In this embodiment, a P-channel MOS transistor is interposed after each of the odd-numbered inverters. For example, a P-channel MOS transistor is interposed only after the last inverter 14E. However, the effects of the present invention can be achieved, and the number of elements can be reduced.

Furthermore, in this embodiment, an embodiment using a NAND circuit as a logic circuit constituting a clock generating circuit has been described. However, the present invention is not limited to this. For example, a NOR circuit may be used as a logic circuit. Can also be applied to a clock generation circuit using the same. In this case, an N-channel MOS transistor is interposed instead of the P-channel MOS transistor.

[0017]

According to the present invention, after the odd-numbered inverters constituting the delay circuit in the clock generation circuit, the change of the pulse waveform of these inverters from high level to low level is determined by the P-channel MOS transistor. In this configuration, the signal of the delay circuit section is reset and the signal is reset at a high speed, so that the pulse waveform can be clocked up and a pulse waveform that follows the clock can be obtained. Therefore, even if the pulse waveform cycle of the pulse waveform becomes faster, the reset by the pulse waveform is delayed as in the related art, and the problem that the constant pulse waveform is not always output from the waveform change point can be solved. .

Also, P is provided only after the last inverter.
Even with a configuration in which a channel type MOS transistor is interposed,
The number of elements can be reduced without impairing the effects of the present invention.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram showing a clock generation circuit according to an embodiment of the present invention.

FIG. 2 is a pulse waveform diagram of the clock generation circuit according to one embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram showing a conventional clock generation circuit.

FIG. 4 is a pulse waveform diagram of a conventional clock generation circuit.

FIG. 5 is a pulse waveform chart for explaining a conventional problem.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Input signal line 12 NAND circuit 14 Delay circuit 14A Inverter 14B Inverter 14C Inverter 14D Inverter 14E Inverter 15 Inverter 16 Output signal line 17 P-channel MOS transistor 18 P-channel MOS transistor 19 P-channel MOS transistor

Claims (3)

[Claims] An output circuit from an input signal line is inputted to one input terminal, and an output waveform from a signal line branched from the input signal line is inputted to the other input terminal. A logic circuit input through the inverter and a clock generation circuit in which an output waveform from the logic circuit is output via an inverter;
A clock generation circuit, comprising a P-channel MOS transistor for resetting a signal of a delay circuit portion in response to a change in a pulse waveform of the inverter from a high level to a low level. 2. A delay circuit comprising an inverter of an odd-numbered stage in which an output waveform from an input signal line is input to one input terminal and an output waveform from a signal line branched from the input signal line is input to the other input terminal. And a clock generating circuit that outputs an output waveform from the logic circuit via an inverter, as viewed from the final stage inverter constituting the delay circuit.
After the n-th (n = 1, 2, 3,...) inverter, a P-channel MOS transistor that resets the signal of the delay circuit portion in response to a change in the pulse waveform of the inverter from a high level to a low level A clock generation circuit characterized by interposing a clock signal. 3. A delay circuit comprising an inverter having an odd-numbered stage in which an output waveform from an input signal line is inputted to one input terminal and an output waveform from a signal line branched from the input signal line is inputted to the other input terminal. A logic circuit input through the inverter and a clock generation circuit that outputs an output waveform from the logic circuit through an inverter. After the odd-numbered stage inverter forming the delay circuit, the pulse waveform of the inverter is A clock generation circuit including a P-channel MOS transistor for resetting a signal of a delay circuit portion in response to a change from a high level to a low level.