GB2119193A

GB2119193A - CMOS buffer amplifier

Info

Publication number: GB2119193A
Application number: GB08310597A
Authority: GB
Inventors: Yuichi Matsuzaki; Suguru Yamazaki
Original assignee: Suwa Seikosha KK
Current assignee: Suwa Seikosha KK
Priority date: 1982-04-28
Filing date: 1983-04-19
Publication date: 1983-11-09
Also published as: DE3314655A1; GB8310597D0; JPS58188931A

Abstract

A CMOS buffer amplifier comprises a driving circuit consisting of a first P-channel transistor (8) and a first N-channel transistor (9), a first inverter (6) whose output is connected to the first P-channel transistor, and a second inverter (7) whose output is connected to the first N- channel transistor. The first inverter consists of a second P-channel transistor and a second N-channel transistor whose amplification factor is smaller than that of the second P- channel transistor. The second inverter consists of a third P-channel transistor and a third N-channel transistor whose amplification factor is greater than that of the third P- channel transistor. The second and third transistors are so arranged to avoid the first P-channel transistor and the first N-channel transistor being in the ON state simultaneously. <IMAGE>

Description

SPECIFICATION CMOS buffer amplifier This invention relates to CMOS buffer amplifiers.

According to the present invention there is provided a CMOS buffer amplifier comprising: a driving circuit consisting of a first P-channel transistor and a first N-channel transistor; a first inverter whose output is connected to said first P-channel transistor; and a second inverter whose output is connected to said first N-channel transistor, said first inverter consisting of a second P-channel transistor and a second N-channel transistor whose amplification factor is smaller than that of the second P-channel transistor, said second inverter consisting of a third P-channel transistor and third N-channel transistor whose amplification factor is greater than that of the third P-channel transistor, said second and third transistors being so arranged to avoid said first P-channel transistor and said first Nchannel transistor being in the ON state simultaneously.

The invention is illustrated, merely by way of example, in the accompanying drawings, in which: Figure 1(a) is a circuit diagram of a conventional CMOS buffer amplifier; Figure 1(b) is a timing chart illustrating the operation of the conventional CMOS buffer amplifier of Fig. 1 a; Figure 2(a) is a circuit diagram of an embodiment of a CMOS buffer amplifier according to the present invention; and Figure 2(b) is a timing chart illustrating the operation of the CMOS buffer amplifier of Fig.

2(a).

Fig. 1 (a) illustrates a conventional CMOS buffer amplifier. A P-channel transistor 4 and an N-channel transistor 5 constitute an output driver circuit of a CMOS buffer amplifier and are driven by respective circuits 2, 3. The circuit 2 is an OR gate and the circuit 3 is an AND gate. The circuits 2, 3 apply signals to the transistor 4 and the transistor 5 so that both transistors 4, 5 are in the OFF state for a given period of time. A delayed flip-flop circuit 1, which is driven by a clock signal f0, delays an input data signal X by as much as one cycle of the clock signal and generates an output signal W. The input data signal X and the output signal W are applied to the circuits 2, 3 which generate respective output signals A, B which are applied to the transistors 4, 5.

As shown by the timing chart of Fig. 1(b), the signals A, B are such that both transistors 4, 5 are in the OFF state during time periods T1, T2. The simultaneous OFF state of both the transistors prevents a short-circuit current from flowing through the transistors 4, 5 between VD and V55 when the level of an output signal Y is changed.

Whilst the conventional CMOS buffer amplifier of Fig. 1 (a) reduces or prevents shortcircuits, it has a considerably large number of components. Moreover, in order to obtain the output signal Y with a precise pulse width, one cycle of the clock signal +0, which is applied to the flip-flop circuit 1, must be less than about one-tenth of the pulse width of the output signal Y. This has the effect that it is difficult to lower the power consumption of the conventional CMOS buffer amplifier.

Fig. 2(a) illustrates one embodiment of a CMOS buffer amplifier according to the present invention. This CMOS buffer amplifier has two CMOS inverters 6, 7 instead of the complicated circuitry of the CMOS buffer amplifier shown in Fig. 1(a). In the inverter 6, the amplification factor of a P-channel transistor (not shown) is larger than that of an Nchannel transistor (not shown). When a driving circuit U is fed to the inverter 6, an output signal C shows a relatively gradual fall and a relatively sharp rise as shown by the timing chart of Fig. 2(b). Conversely, in the inverter 7, the amplification factor of an N-channel transistor (not shown) is larger than that of a P-channel transistor (not shown). When the driving signal U is fed to the inverter 7, an output signal D shows a relatively sharp fall and a relatively gradual rise.The output signals C, D delivered from the inverters 6, 7 are delayed relative to the driving signal U. In other words, a P-channel transistor 8 connected to receive the output signal C is in the OFF state during the period from To to T2 and is in the QN state during the period from T2 to T3 and is in the OFF state during the period from T3 to T5. Similarly, an N-channel transistor 9 connected to receive the output signal D is in the ON state during the period from To to T1, in the OFF state during the period from T, to T4 and in the ON state during the period from T4 to T5. Thus both transistors 8, 9 are in the OFF state during the periods from T1 to T2 and from T3 to T4.The length of these periods in which both transistors 8, 9 are in the OFF state and the delay time of the transistors of the inverters 6, 7 are of the order of seconds.

By providing periods of time when both transistors 8, 9 are in the OFF state, there is no opportunity of a short-circuit flowing through the transistors 8, 9 between VDD and V55 when the level of an output signal V is changed.

The conventional CMOS buffer amplifier of Fig. 1 (a) has a relatively large number of transistors for generating the signals applied to the transistors 8, 9. On the other hand the CMOS buffer amplifier of Fig. 2(a) prevents short-circuit current so long as the two signals applied to the transistors 8, 9 have different delay times and are not both ON simultaneously. Thus, the CMOS buffer amplifier of Fig.

2(a) has relatively few transistors and any consideration of driving pulse width is not of material importance.

Claims

1. A CMOS buffer amplifier comprising: a driving circuit consisting of a first p-channel transistor and a first N-channel transistor; a first inverter whose output is connected to said first P-channel transistor; and a second inverter whose output is connected to said first N-channel transistor, said first inverter consisting of a second P-channel transistor and a second N-channel transistor whose amplification factor is smaller than that of the second p-channel transistor, said second inverter consisting of a third P-channel transistor and a third N-channel transistor whose amplification factor is greater than that of the third P-channel transistor, said second and third transistors being so arranged to avoid said first P-channel transistor and said first Nchannel transistor being in the ON state simultaneously.

2. A CMOS buffer amplifie substantially as herein described with reference to Figs.

2(a) and 2(b) of the accompanying drawings.