JPH066210A - Timer circuit - Google Patents

Abstract

PURPOSE:To provide a timer circuit which has a noise dealing function to the external input signals. CONSTITUTION:A selection circuit 7 sets and outputs the initial value to a counter circuit 1 from a reload register 3 in response to an external input signal. Meanwhile an input control circuit 8 outputs the initial value to the circuit 1 in response to the AND secured between an event input signal and the external input signal. Therefore the circuit 1 outputs an overflow signal based on the initial value set previously and in response to the H-level period of the external input signal. Based on this overflow signal, a pulse that has a short H-level period to the external input signal and has many noise components due to the chattering, etc., is discriminated from a pulse that has a long H-level period and has the reduced noise components.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timer circuit composed of a semiconductor circuit.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional timer circuit. In the figure, 1 is a counter circuit which counts in synchronization with an event input signal input from an event input terminal 2 and 3 is a counter circuit 1. Reload register that sets and outputs the stored value by overflow signal,
Reference numeral 4 is an output signal line of the counter circuit 1, and 5 is a bus connecting a central processing unit (not shown, hereinafter referred to as CPU) to the counter circuit 1 and the reload register 3.

Next, the operation will be described. in advance,
Data is supplied from the CPU to the counter circuit 1 and the reload register 3 via the bus 5 as initial values. Next, the counter circuit 1 increases or decreases the counter value in synchronization with the event input signal input from the event input terminal 2 based on this initial value. For example, if the counter circuit 1 is an 8-bit up counter, the counter value is "00".
To "FF" increase by +1. Then, when the next event is input when the counter value is "FF", the counter circuit 1 overflows in synchronization with the output of the overflow signal. By this overflow signal, the reload register 3 sets and outputs the value stored in the reload register 3 as an initial value to the counter circuit 1. The counter circuit 1 again increases the counter value in synchronization with the event input signal based on the set and output initial value.

[0004]

Since the conventional timer circuit is configured as described above, a periodic output signal corresponding to the initial value given by the CPU is obtained from the output signal line 4 of the counter circuit 1. It is possible, but like this,
Since it has a single function, its application is limited. For example, there is a problem that noise countermeasures cannot be taken, such as distinguishing between a pulse having a long H level period and a large noise component due to chattering and a pulse having a long H level period and a small noise component with respect to an external input signal. It was

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a timer circuit having a function of preventing noise of an external input signal.

[0006]

A timer circuit according to the present invention comprises a selection circuit for selecting either an overflow signal of a counter circuit or an external input signal and outputting the selected signal to a reload register, an event input signal and an external input signal. And an input signal control circuit for outputting a signal according to the logical product of

[0007]

In the timer circuit according to the present invention, by selecting the selection circuit to the external input signal side, the initial value preset according to the external input signal is set and output from the reload register to the counter circuit. The input signal control circuit inputs the event input signal and the external input signal and outputs a signal corresponding to the logical product of them to the counter circuit. Therefore, the counter circuit outputs an overflow signal according to the length of the constant level period of the external input signal based on the preset initial value, and the overflow signal causes the constant level period with respect to the external input signal. A short signal with many noise components and a signal with a long fixed level period and few noise components are discriminated.

[0008]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 to 5 are equivalent to the conventional technique. Reference numeral 6 designates an external input terminal for inputting an external input signal on which a noise component is superimposed, 7 designates either the overflow signal of the counter circuit 1 or the external input signal input from the external input terminal 6, and selects the signal line A Output to the reload register 3 via the selection circuit 7
Are connected to a CPU (not shown) by a bus 5. Reference numeral 8 denotes a counter circuit 1 which outputs a signal corresponding to a logical product of an event input signal input from the event input terminal 2 and an external input signal.
It is an input signal control circuit for outputting to. In addition, B indicates a signal line from the selection circuit 7 to the input signal control circuit 8.

Next, the operation will be described. This will be described with reference to the block diagram of FIG. 1 and the timing chart of FIG. First, the counter circuit 1 via the bus 5 by the CPU
An initial value “AA” is given to the reload register 3, for example. Also, the CPU is set to select the selection circuit 7 to the external input signal side. This selection circuit 7 causes the reload register 3 to receive an external input signal (FIG. 2 (A)).
2B is output through the signal line A, and the rising edges t ₁ , t ₂ , t of the external input signal in FIG.
_The reload register 3 sets and outputs "AA" stored as an initial value to the counter circuit 1 in accordance with ₃ and t ₄ . At this time, in the case of a pulse having a short H level period such as the external input signals t _{1 to} t ₄ , the reload register 3 causes the counter circuit 1 to move.
The set output interval is short and the set output interval is long for a pulse having a long H level period such as after t ₄ . The selection circuit 7 outputs an H level signal (FIG. 2C) from the signal line B to the input signal control circuit 8 in accordance with the selection on the external input signal side.

Further, the input signal control circuit 8 receives the event input signal input from the event input terminal 2 (see FIG. 2).
(D)) and the external input signal input from the external input terminal 6 are input and output to the counter circuit 1 according to the logical product of them (FIG. 2 (E)). At this time, the event input signal number of H level is output to the counter circuit 1 is less than H-level period is short pulse as an external input signal t ₁ ~t _4, a long H-level period, such as t ₄ after Increased with pulses.

Further, as shown in FIG. 2F, in the counter circuit 1, "AA" is set as an initial value from the reload register 3 at time t ₁ . In addition, the input signal control circuit 8
Further, an event input signal which is a logical product of an external input signal is input, and the initial value "AA" is counted by +1.
However, since the H level period of the external input signal is short, the counter value of the counter circuit 1 does not increase, the overflow value “FF” is not reached, and “AA” is set as the initial value from the reload register 3 at time t _2. It Similarly, the counter circuit 1 counts by the event input signal after the time t _2, but the overflow value “FF” does not reach until the time t ₄ because the H level period of the external input signal is short.

Since the H level period is long after time t ₄ ,
The counter value of the counter circuit 1 increases, and after reaching the overflow value “FF”, an overflow signal is output from the output signal line 4 of the counter circuit 1. By using this overflow signal as an interrupt signal of the CPU, the external input signal can be interrupted from time t ₄ . In this way, it is possible to distinguish between a pulse having a short H level period and a large noise component and a pulse having a long H level period and a small noise component with respect to the external input signal.

FIG. 3 is a logic circuit diagram showing a specific configuration of the input signal control circuit 8. In the figure, 9a is a nut gate, 9b is a NAND gate, and 9c is an AND gate.
With the configuration shown in FIG. 3, when the selection circuit 7 selects the external input signal side, an H level signal is input to the selection circuit output signal B, and the logical product of the external input signal and the event input signal is counted. It is output to the circuit 1. In addition, the selection circuit 7
When the overflow signal side of the counter circuit 1 is selected, the L level signal is input to the selection circuit output signal B, and the event input signal is output to the counter circuit 1 as it is. Therefore, this timer circuit can select the same function as that of the prior art by the selection circuit 7.

[0014]

As described above, according to the present invention, the selection circuit for selecting either the overflow signal of the counter circuit or the external input signal and outputting it to the reload register, the event input signal and the external input signal are selected. Since the input signal control circuit that outputs a signal corresponding to the logical product to the counter circuit is provided, a constant level period is short with respect to an external input signal due to an overflow signal of the counter circuit, and a noise component is large due to chattering or the like. It is possible to distinguish a signal from a signal having a long fixed level period and a small noise component, and it is possible to obtain a timer circuit having a noise countermeasure function for an external input signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a timer circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of a main part of FIG.

FIG. 3 is a logic circuit diagram showing a specific configuration of an input signal control circuit.

FIG. 4 is a block diagram showing a conventional timer circuit.

[Explanation of symbols]

 1 counter circuit 3 reload register 7 selection circuit 8 input signal control circuit

Claims (1)

[Claims] 1. A timer circuit comprising: a counter circuit that counts in synchronization with an event input signal; and a reload register that sets and outputs a stored value to the counter circuit according to an overflow signal of the counter circuit. A selection circuit that selects either the circuit overflow signal or the external input signal and outputs it to the reload register, and the input signal control that outputs a signal according to the logical product of the event input signal and the external input signal to the counter circuit. And a timer circuit.