JPH0821844B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous bus type semiconductor integrated circuit for inputting and outputting a signal to be input / output without using a clock signal, and particularly to two types of control signals. The present invention relates to a semiconductor integrated circuit in which the number of terminals can be reduced by allocating each to one terminal.

[Prior Art] In an asynchronous bus type semiconductor integrated circuit, when two types of control signals are to be assigned to one terminal, for example, a circuit as shown in FIG. 3 can be considered.

In the figure, 1 is a chip select signal for chip selection
The chip select terminal 2 to which CS is input has two first and second logic level periods, which are one of the first and second circuit operations that cause the semiconductor integrated circuit to perform the first and second circuit operations, respectively.
One control terminal for receiving the control signal A / of 4 and 3 is generated based on the chip select signal and the first control signal, and the semiconductor integrated circuit of the present invention performs the first and second circuit operations. An internal control signal line for transmitting the second and third control signals A'and B ', an AND gate 8 for ANDing the first control signal and the chip select signal to generate a second control signal A', 1
0 is an inverter that inverts the first control signal, 7 is an output of the inverter 10, that is, an AND gate that ANDs the inverted signal of the first control signal and the chip select signal to generate the third control signal B ′. is there.

FIG. 4 shows an example of the timing of the circuit of FIG.

As shown in FIG. 4, in order to activate the internal control signal A ', both the chip select terminal 1 and the control terminal 2 may be set to "H".

However, when the input CS of the chip select terminal 1 is longer than the input A / period t1 of the control terminal 2 as shown in FIG. 4 when the internal control signal A'is made active, the internal control signal line 3 The output B'has an error during the t2 and t3 periods. This error is fatal because the "H" signal is erroneously output to the output B'of the internal control signal line 3 when only the output A'of the internal control signal line 4 is activated from the outside. It is an error.

[Problems to be solved by the invention]

Due to such a problem, conventionally, in the asynchronous bus type semiconductor integrated circuit, it was impossible to allocate two control signals to one terminal.

The present invention has been made in order to solve the problems of the conventional ones described above. Even though it is an asynchronous bus type, it is possible to allocate two control signals to one terminal. It is an object of the present invention to obtain a semiconductor integrated circuit capable of reducing

[Means for solving problems]

The semiconductor integrated circuit according to the present invention receives one first control signal for causing the semiconductor integrated circuit to perform the first and second circuit operations during the periods of the first and second logic levels, respectively. A logical product of two control terminals, a chip select signal for chip selection that becomes significant at the first logic level, and the first control signal is obtained, and a period of the first logic level causes the semiconductor integrated circuit to operate. A first AND gate for generating a second control signal for performing the first circuit operation, a delay circuit for delaying the first control signal for a predetermined time, and a first control signal and the delay circuit. A NOR circuit that generates a NOR signal with the output signal is ANDed with the output signal of the NOR circuit and the chip select signal. Third to perform circuit operation A second AND gate for generating a control signal, wherein the second circuit operation is performed when the chip select signal is significant and the first circuit operation is switched to the second circuit operation. Third
The control signal is forbidden from generating a false signal.

[Action]

According to the present invention, the configuration as described above allows the second circuit operation to be performed when the chip select signal is significant and the first circuit operation is switched to the second circuit operation. It is prohibited to generate a false signal in the control signal of No. 3, and the second control signal and the second control signal can be separated from one first control signal without causing a malfunction of the circuit. It becomes possible to assign the control signal of 1 to one terminal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor integrated circuit according to an embodiment of the present invention. This embodiment prohibits malfunctions during a period t3 in FIG. In FIG. 1, 1
Is a chip select terminal to which a chip select signal CS for chip selection is input, and 2 is a semiconductor integrated circuit that performs the first and second circuit operations during the periods of the first and second logic levels, respectively. One control terminal for receiving one first control signal A /, 4 and 3 are the first and second circuits which are generated based on the chip select signal and the first control signal. An internal control signal line for transmitting the second and third control signals A'and B'for carrying out the operation, 8 is a logical product of the first control signal and the chip select signal to generate the second control signal A '. AND gate, 5 is a delay circuit that delays the first control signal for a predetermined time, 6 is a NOR gate that generates a NOR signal between the first control signal and the output of the delay circuit 5, and 7 is
It is an AND gate that produces the third control signal B ′ by taking the logical product of the output of the NOR gate 6 and the chip select signal.

FIG. 2 shows the timing of the circuit of FIG.

Next, the operation will be described. As described above, the signal B ′ causes an error when the timing shift occurs between the CS signal and the A / B signal. In this embodiment, the error is
The signal a / after passing through the delay circuit 5 is rejected as shown in FIG. 2 by taking the NOR of the signal a and the A / signal itself, and the AND of the signal b and the CS signal. The time constant of the delay circuit may be determined in consideration of the maximum value of the CS signal shift that can occur in the system and the pulse width of the control signal A /. As described above, according to the above-described embodiment, the chip select signal for bringing the chip into the selected state, and its logic high level and logic low level in the active state of the chip select signal are respectively the first and second internal logics. One logic signal corresponding to the active state of the signal is input, the logical product of this chip select signal and the logic signal is taken to generate the first internal logic signal, and the logic signal is delayed for a predetermined time and the original The logical sum of the logical signals is logically inverted, and the logical product is further ANDed with the chip select signal to generate the second internal logical signal, and the control is performed by the first and second internal logical signals. Therefore, the number of terminals of the asynchronous bus type semiconductor integrated circuit can be reduced, and the cost can be reduced. It is also possible to assign other functions to the vacant pins,
The performance can be improved.

〔The invention's effect〕

As described above, according to the semiconductor integrated circuit of the present invention, one of the first and second logic level periods causes the present semiconductor integrated circuit to perform the first and second circuit operations, respectively. One control terminal for receiving a control signal of 1 and a chip select signal for chip selection which becomes significant at the first logic level and the first control signal are logically ANDed, and a period of the first logic level is A first AND gate for generating a second control signal for causing the present semiconductor integrated circuit to perform a first circuit operation; a delay circuit for delaying the first control signal for a predetermined time; A NOR circuit that generates a NOR signal between the control signal and the output signal of the delay circuit is ANDed with the output signal of the NOR circuit and the chip select signal, and the period of the first logic level is the present semiconductor integrated circuit. Circuit and second circuit The chip select signal is significant, and the second circuit operation is switched from the first circuit operation to the second AND gate for generating the third control signal for performing the operation. Occasionally, it is possible to prevent a false signal from being generated in the third control signal that causes the second circuit operation to be performed.
The control signal and the second control signal can be separated, and there is an effect that two control signals can be assigned to one terminal.

[Brief description of drawings]

1 is a diagram showing a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a timing chart diagram of the circuit of FIG. 1,
FIG. 3 is a diagram showing a conventional semiconductor integrated circuit, and FIG.
It is a timing chart figure of a figure. In the figure, 1 is a chip select terminal, 2 is a control terminal,
3 is an internal control signal, 4 is an internal control signal, 5 is a delay circuit,
6 is a NOR gate, 20 is a prohibition circuit, 7 and 8 are AND gates,
CS is chip select terminal input, A / B is control terminal input, a
Is a delay circuit output, b is a NOR circuit output, and A'and B'are internal control signals. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A control terminal for receiving a first control signal for causing the semiconductor integrated circuit to perform a first and a second circuit operation, respectively, during a period of the first and second logic levels. , A logical product of a chip select signal for chip selection which becomes significant at the first logic level and the first control signal is obtained, and a period of the first logic level causes the semiconductor integrated circuit
For generating a second control signal for performing the circuit operation of
An AND gate, a delay circuit that delays the first control signal for a predetermined time, a NOR circuit that generates a NOR signal of the first control signal and the output signal of the delay circuit, and an output signal of the NOR circuit. And a chip select signal, and a second AND gate for generating a third control signal for causing the semiconductor integrated circuit to perform the second circuit operation during the period of the first logic level. And a false signal is generated in the third control signal that causes the second circuit operation when the chip select signal is significant and the first circuit operation is switched to the second circuit operation. A semiconductor integrated circuit characterized by prohibiting