JP2765835B2 - Signal detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal detection circuit, and more particularly, to a signal detection circuit that detects an input signal having a predetermined time width or more. [Prior Art] Conventionally, as a signal detection circuit of this type, there has been one as shown in FIG. 7 or FIG. 9, for example. Basically, one of the two inputs NOR34,44 is connected to input terminals 31,41, and the other input is connected from the input terminal via delay circuits 36,47 and NOR37 for signal inversion or inverter 47. It is. In the circuit shown in FIG. 7, the TOR 38 is connected to the NOR 37 in such a manner as to form a flip-flop, and the output from the first output terminal 32 is fed back to the flip-flop. In each of the circuits shown in FIGS. 7 and 9, the output is taken directly from the NORs 34 and 44. It has a first output terminal and second output terminals 33, 43 which are taken out as inverted outputs via inverters 35, 45. Next, the operation of the circuit of FIG. 7 will be described. For simplicity of explanation, the delay time of the delay circuit 36 is set to a value sufficiently larger than the delay time of one stage of the gate. First, consider a case where a signal having a time width longer than the delay time of the delay circuit 36 is input to the input terminal 31 as shown in FIG. The input signal is high, that is, the input terminal 31
Is high, the outputs of the two-input NORs 34 and 37 and the delay circuit 36 are low, and the output of the two-input NOR 38 is high. When the input signal changes from the high state to the low state, the output of the 2-input NOR 34, that is, the output terminal 32, changes from the low state to the high state, and the output of the 2-input NOR 38 changes from the high state to the low state, and the output of the 2-input NOR 37 changes to the low state. To a high state, this output is delayed via a delay circuit 36, input to the two-input NOR 34, and the output of the two-input NOR 34, that is, the output terminal 22 sequentially changes to the low state again. Therefore, the first
A high state corresponding to the delay time of the delay circuit 36 is obtained at the output terminal 32 of FIG. When the input signal changes from the low state to the high state, the output of the two-input NOR 34 remains low and the output of the two-input NOR 37 changes from the high state to the low state.
The output of OR38 changes from the low state to the high state, and the 2-input NOR3
The output of 7 is delayed via the delay circuit 36 and input to the 2-input NOR 34. Next, consider a case where a signal having a pulse width shorter than the delay time of the delay circuit 36 is input to the input terminal 31 as shown in FIG. When the input signal is in the high state, the operation is the same as described above. When the input signal changes from the high state to the low state, the output of the two-input NOR 34, that is, the first output terminal 32 changes from the low state to the high state, and the output of the two-input NOR 38 changes from the high state to the low state. The output of the input NOR37 changes from a low state to a high state. When the input signal changes from the low state to the high state, the output of the three-input NOR 34, that is, the first
The output terminal 32 of the second input NOR 37 changes from the high state to the low state, the output of the two-input NOR 37 changes from the high state to the low state, and the output of the two-input NOR 38 changes from the low state to the high state. The output of the delay circuit 36 changes from a low state to a high state and further from a high state to a low state with a delay of the delay time. Therefore, the first output terminal 32
Provides an inverted signal of the input signal. In this manner, a signal having a pulse width shorter than a predetermined time for an input signal having an arbitrary pulse width is output to the first output terminal 32, and the input signal can be detected. Also, the second
The output terminal 33 of the first output terminal 32
Can be obtained. Next, the operation of the circuit of FIG. 9 will be described. In describing the operation, the delay time of the delay circuit 46 is set to a value sufficiently larger than the delay time of one stage of the gate, as described above. As shown in FIG. 10 (a), a delay circuit 46 is connected to the input terminal 41.
Consider a case where a signal having a time width longer than the delay time is input. When input signal is high, 2-input NOR44
Is in a low state, the delay circuit 46 is in a high state, and the output of the inverter 47 is in a low state. When the input signal changes from the high state to the low state, the output of the two-input NOR 44, that is, the first output terminal 42 changes from the low state to the high state, the input signal is delayed via the delay circuit 46, and the high state changes to the low state. , The output of the inverter 47 changes from the low state to the high state, and the two-input NO
The output of R44, that is, the first output terminal 42 changes from the high state to the low state again. Accordingly, a high state corresponding to the delay time of the delay circuit 46 is obtained at the first output terminal 42. Also,
When the input signal changes from low to high, two inputs
The output of NOR44 remains low and the input signal is
From the low state to the high state, the inverter 47
Changes from a high state to a low state. Next, consider a case where a signal having a pulse width shorter than the delay time of the delay circuit 46 is input to the input terminal 41 as shown in FIG. 10 (b). When the input signal is in the high state, it is the same as described above. When the input signal changes from the high state to the low state, the output of the two-input NOR 44, that is, the first output terminal 42 changes from the low state to the high state, and when the input signal changes from the low state to the high state, the output of the two-input NOR 44 That is, the first
Changes from the high state to the low state. Delay circuit
At the output of 46, the input signal appears in phase with the delay time, and its inverted output becomes the output of the inverter 47. In this manner, a signal having a pulse width shorter than a predetermined time is output from the first output terminal 42 with respect to an input signal having an arbitrary pulse width, and the input signal can be detected. The second output terminal 43 is connected to the first output terminal by an inverter 45.
42 inverted outputs can be obtained. [Problems to be Solved by the Invention] The conventional signal detection circuit described above outputs a signal having a pulse width of a predetermined time or less for an input signal having an arbitrary pulse width, and can detect the input signal. However, since the signal is detected even if the pulse width of the input signal is small, the device operates even with impulse-like noise, and the noise is detected as an input signal, and the entire system malfunctions. . [Means for Solving the Problems] A signal detection circuit according to the present invention comprises an input terminal for receiving an input pulse signal, a first input connected to the input terminal, and a second input terminal.
, A third input and an output terminal, wherein the first,
A gate circuit that sets the output terminal to one logic level when the second and third inputs assume a first logic level, and sets the output terminal to the other logic level when at least one takes the second logic level. A flip-flop circuit having one input terminal connected to the input terminal and the other input terminal connected to the output terminal; and a first flip-flop circuit connected to the input terminal and delaying the input pulse signal by a first time. Means for supplying the delayed pulse signal to the second input of the gate circuit;
Means for supplying a second delayed pulse signal delayed by the time period to the third input of the gate circuit. In other words, the conventional signal detection circuit can detect an input signal having a small pulse width, so that even an impulse-like noise is detected as a signal. Unless the input signal has a width, it cannot be detected as a signal, so that malfunctions can be prevented with respect to impulsive noise. Next, the present invention will be described with reference to the drawings. FIG. 1 shows a signal detection circuit according to an embodiment of the present invention. In the drawing, a three-input NOR4 has one input directly connected to the input terminal 1, the other input connected to the input terminal 1 via the delay circuit 9, and the other input connected to the delay circuit 6, the NOR7 and the NOR7. And the output is connected to the first output terminal 2 and to the second output terminal 3 via the inverter 5. Next, the operation will be described. For simplicity of explanation, the delay time of the delay circuits 6 and 9 is set to a value sufficiently larger than the delay time per gate stage. First, consider a case where a signal having a time width longer than the delay time of the delay circuit 9 is input to the input terminal 1 as shown in FIG. The input signal is high, that is, input terminal 1
Is high, the three-input NOR4, two-input NOR7 and the output of the delay circuit 6 are low, and the two-input NOR8 and the delay circuit 9
Is in a high state. When the input state changes from the high state to the low state, the output of the delay circuit 9 changes from the high state to the low state with a delay of the delay time, and the output of the three-input NOR4, that is, the output terminal 2, changes from the low state to the high state. input
The output of NOR8 changes from a high state to a low state, and the output of NOR2 changes from a low state to a high state.
, And is input to the three-input NOR4, and the output of the three-input NOR4, that is, the output terminal 2 sequentially changes to the low state again. Therefore, a high state corresponding to the delay time of the delay circuit 6 is obtained at the first output terminal 2. When the input signal changes from the low state to the high state, the output of the three-input NOR4 remains in the high state, the output of the two-input NOR7 changes from the high state to the low state, and the output of the two-input NOR8 changes from the low state to the high state. The output of the two-input NOR 7 is delayed via the delay circuit 6 and input to the three-input NOR 4, while the input signal is delayed via the delay circuit 9 and input to the three-input NOR 4. Next, a case where a signal having a pulse width shorter than the delay time of the delay circuit 9 is input to the input terminal 1 as shown in FIG. When the input signal is in the high state, it is the same as described above. When an input signal with a short pulse width is input to the input terminal 1, the delay time of the delay circuit 9 is longer than the pulse width, so that the input signal and the output of the delay circuit 9 are not simultaneously in a low state, so that the output of the three-input NOR4, The first output terminal 2 holds a low state. Therefore, the output of the two-input NOR8 is in the high state, and the output of the two-input NOR7 and the delay circuit 6 is in the low state. In this manner, an input signal can be detected only when an input signal having a pulse width equal to or more than a certain time width is input to the output terminal 2. The second output terminal 3 can obtain an inverted output of the first output terminal 2 by the inverter 5. Next, a first reference example of the present invention will be described. FIG. 3 shows a signal detection circuit according to a first reference example of the present invention. In the figure, a three-input NOR 14 connects one input to an input terminal 1
1, the other one is connected to an input terminal via a delay circuit 18, and the other input is connected to an input to which the delay circuit 18 is connected via an inverter 17 and a delay circuit 16. Connected. In the description of the operation, the delay times of the delay circuits 16 and 18 are set to be sufficiently larger than the delay time of one gate, as described above. As shown in FIG. 4A, a delay circuit 18 is connected to the input terminal 11.
Consider a case where a signal having a time width longer than the delay time is input. When the input signal is high, the delay circuit 16
The output of 18 is in the high state, the output of inverter 17 and the 3-input NOR1
The output of 4 is low. When the input signal changes from the high state to the low state, the output of the delay circuit 18 changes from the high state to the low state with a delay of the delay time, and the output of the three-input NOR 14, that is, the first output terminal 12 changes from the low state to the high state. Become. The output of the delay circuit 18 is delayed via the delay circuit 16 and changes from the high state to the low state, the output of the inverter 17 changes from the low state to the high state, and the output of the three-input NOR 14 changes to the low state again. Therefore, a high state corresponding to the delay time of the delay circuit 16 is obtained at the first output terminal 12. When the input signal changes from the low state to the high state, the delay circuit 18
Output from the low state to the high state after a delay time, and this output signal is delayed via the delay circuit 16 to change from the low state to the high state. The output of the inverter 17 changes from the high state to the low state. The output of NOR14 holds a low state. Next, as shown in FIG. 4B, a case where a signal having a pulse width shorter than the delay time of the delay circuit 18 is input to the input terminal 11 will be considered. When the input signal is in the high state, it is the same as described above. When an input signal having a short pulse width is input to the input terminal 11, the delay time of the delay circuit 18 is longer than the pulse width, so that the input signal and the output of the delay circuit 18 are not simultaneously in a low state. The first output terminal 12 holds a low state. The output of the delay circuit 18 is delayed via the delay circuit 16, inverted by the inverter 17, and becomes the input of the three-input NOR 14. In this manner, an input signal can be detected only when an input signal having a pulse width longer than a certain time is input to the first output terminal 12. Also, the second output terminal 13
Can obtain an inverted output of the output terminal 2 by the inverter 15. FIG. 5 shows a signal detection circuit according to a second embodiment of the present invention. In the figure, a three-input NOR24 connects one input to input terminal 2
1, the other input is connected to the input terminal 21 via the delay circuit 28, and the other input is connected to the inverter 27.
And a delay circuit 26 to the input terminal 21. Here, if the delay time of the delay circuit 26 is made longer than the delay time of the delay circuit 28, the operation is exactly the same as in FIG. 3 of the first reference example. Delay circuit 26 and delay time at first output terminal 22
6 except that a high state is obtained by a delay time difference from the delay circuit 28, but by making this delay time difference equal to the delay time of the delay circuit 16 in FIG.
As shown in (b), the operation of the second reference example is completely equivalent to that of the first reference example. [Effects of the Invention] As described above, the present invention provides an OR circuit for an input signal, an inverted signal obtained by delaying and inverting the input signal, and a delay signal obtained by delaying the input signal. To obtain the output from this OR circuit,
A hazard having a short pulse width, such as an impulse-shaped noise having a certain width or less, is not detected, so that there is an effect that a malfunction can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 (b) is a waveform diagram for explaining the operation of the circuit of FIG. 1, FIG. 3 is a circuit diagram showing a first embodiment of the present invention, and FIGS.
(B) is a waveform diagram illustrating the circuit operation of FIG. 2, FIG. 5 is a circuit diagram showing a second reference example of the present invention, and FIGS.
(B) is a waveform diagram for explaining the operation of the circuit shown in FIG. 5, FIG. 7 is a circuit diagram showing a conventional signal detection circuit, and FIGS.
(B) is a waveform diagram illustrating the operation of the circuit of FIG. 7, FIG. 9 is a circuit diagram showing another conventional signal detection circuit, and FIGS. 10 (a) and (b) are diagrams of the circuit of FIG. FIG. 6 is a waveform diagram illustrating an operation. 1, 11, 21, 31, 41 ... input terminal, 2, 12, 22, 32, 42 ... first output terminal, 3, 13, 23, 33, 43 ... second output terminal, 4, 14,24
…… Normal NOR, 7,8,34,37,38,44 …… Normal NOR, 5,15,
17,25,27,35,45,47 …… Inverter, 6,9,16,18,26,28,3
6,46 …… Delay circuit.

Claims (1)

(57) [Claims] An input terminal for receiving an input pulse signal; a first input, a second input, a third input, and an output terminal connected to the input terminal, wherein the first, second, and third inputs are A gate circuit that sets the output terminal to one logic level when the logic level is 1, and sets the output terminal to the other logic level when at least one takes the second logic level; A flip-flop circuit connected to the input terminal and having the other input terminal connected to the output terminal; and a first delayed pulse signal connected to the input terminal and delaying the input pulse signal by a first time. Means for supplying to the second input, and means for supplying, to the third input of the gate circuit, a second delayed pulse signal obtained by delaying the signal held in the flip-flop circuit by a second time. Prepare No. detection circuit.