JPH0156406B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention provides a clock switching circuit, particularly a clock signal generation circuit and a clock switching circuit, each of which has a clock signal generation circuit and a clock switching circuit. This article relates to a clock switching circuit in a dual system that is used in both systems at the same time.

(b) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional clock switching circuit of this kind, and FIG. 2 is a diagram showing an example of the clock switching process in FIG. 1. In FIG. 1, a clock signal generating circuit 1 and a clock switching circuit 3 belong to one system in a dual system, and a clock signal generating circuit 2 and a clock switching circuit 4 belong to the other system. The clock switching circuits 3 and 4 select either the clock signal a1 output from the clock signal generation circuit 1 or the clock signal a2 output from the clock signal generation circuit 2 based on the designation of the input switching signals b1 or b2, respectively. One of them is selected at the same time and supplied to each system as the output clock signal d1 or d2. The clock switching circuit 3 supplies the clock signal a1 outputted from the clock signal generation circuit 1 within its own system to the own system as an output clock signal d1 when the input switching signal b1 indicates a logical value of 1. When the switching signal b1 indicates a logical value of 0, the clock signal a2 outputted from the clock signal generation circuit 2 in the ground system is supplied to the own system as the output clock signal d1. Similarly, clock switching circuit 4
Depending on the logic value indicated by the switching signal b2, the clock signal a2 or a1 is supplied within the own system as the output clock signal d2. In Figure 2, switching signal b
1 is set to the logical value 1, and the switching signal b2 is set to the logical value 0. In the clock switching circuit 3, the switching signal b1 is applied to the terminal D of the flip-flop 301 via the gate 302 which is in a conductive state.
is input. The flip-flop 301 is set to a set state by the clock signal a1 inputted to the terminal CK via the inverter 303, and sets the output signal c1 outputted from the terminal Q to a logical value of 1.
The output signal c1 makes the gate 304 conductive,
Further, the gate 402 in the clock switching circuit 4 is set to a blocked state, and the gate 407 is set to a conductive state. the result,
In the clock switching circuit 3, the clock signal a1
is supplied to its own system as an output clock signal d1 via gates 304 and 305, and in clock switching circuit 4, clock signal a1 supplied from clock switching circuit 3 via buffer 306 is supplied to gates 407 and 405. The output clock signal d2 is supplied within the own system as the output clock signal d2.
Note that the flip-flop 4 in the clock switching circuit 4
01 is in the reset state and outputs the output signal c2 with a logic value of 0. As a result, the gate 307 in the clock switching circuit 3 and the gate 404 in the clock switching circuit 4 are in the blocking state, and the clock signal a2 becomes the output clock signal d1. and will not be output as d2. In this state, when the switching signal b1 changes to a logic value of 0 and the switching signal b2 changes to a logic value of 1 at time t1, the flip-flop 301 enters a reset state at time t2, changing the output signal c1 to a logic value of 0. As a result, gate 3
04 and 407 are in a blocking state and stop outputting the clock signal a1 as the output clock signals d1 and d2. Also, the output signal c1 has a logical value of 0
As a result, the gate 402 in the clock switching circuit 4 becomes conductive, and the switching signal b2 is input to the terminal D of the flip-flop 401. As a result, the flip-flop 401 is connected to the inverter 403.
Clock signal a2 input to terminal CK via
As a result, the set state is reached at time t3, and the output signal c
Change 2 to logical 1. As a result, gate 307
and 404 become conductive, and the clock signal a
2 are output as output clock signals d1 and d2. In the clock switching circuit 4, the clock signal a2 is directly transmitted to the gate 404, so when the output signal c2 is set to the logical value 1, the clock signal a2 has already changed to the logical value 0, and the clock signal a2 has already changed to the logical value 0 at time t4. Thereafter, the normal clock signal a2 is output as the output clock signal d2, but in the clock switching circuit 3, the clock signal a2 is transmitted to the gate 306 via the buffer 406, so a delay time occurs, and the output signal c2 is After being set to the logic value 1, the clock signal a2 is maintained at the logic value 1 during the delay time, so that at time t
During the period from t3 to t3', an abnormal pulse is output as the output clock signal d1, causing various malfunctions within the own system.

As is clear from the above description, in a conventional clock switching circuit, when switching the output clock signal d1 from the clock signal a1 to the clock signal a2, an abnormal pulse is output based on the delay time of the clock signal a2 passing through the buffer 406. It is output as the clock signal d1 and may cause malfunction in the own system.

(c) Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional clock switching circuits as described above, and to provide a means for preventing the generation of abnormal pulses that may cause system malfunctions during switching. Ru.

(d) Structure of the Invention The object of the present invention is to provide a dual-system system, each equipped with a clock signal generation circuit and a clock switching circuit, in which both systems simultaneously use the clock signal output from one of the clock signal generation circuits. a first flip-flop that operates with a local clock signal output from a clock signal generation circuit in the local system and holds a local switching signal that specifies a clock signal to be supplied to the local system; a second flip-flop that operates and holds the output signal of the first flip-flop; and a first gate that controls supply of the home system clock signal to the home system based on the output signal of the second flip-flop; The third clock operates with the other system clock signal output from the clock signal generation circuit in the other system, and holds the other system switching signal that specifies the clock signal to be supplied to the other system, which is held in the other system clock switching circuit. a fourth flip-flop that operates on the external clock signal and holds the output signal of the third flip-flop; (e ) Embodiment of the Invention An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram showing a clock switching circuit according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of the clock switching process in FIG. 3. In addition,
The same reference numerals indicate the same objects throughout the figures. Third
In the figure, when the switching signal b1 is set to the logical value 1 and the switching signal b2 is set to the logical value 0, the flip-flop 301 to which the switching signal b1 is input to the terminal D via the gate 302 outputs the inverter 30.
Clock signal a input to terminal CK via 3
1 enters the set state, and the output signal c1 output from the terminal Q is set to a logical value of 1. The output signal c1 is input to terminal D of flip-flop 309 and to terminal D of flip-flop 410 in clock switching circuit 4 via buffers 312 and 414, respectively. flipflop 309
is set to the set state by the clock signal a1 input to the terminal CK via the inverter 303,
The output signal e1 output from the terminal Q is set to a logical value of 1. Furthermore, the flip-flop 410 is set to a set state by the clock signal a1 inputted to the terminal CK via the buffers 306 and 413.
The output signal f2 output from the terminal Q is set to a logical value of 1. The output signal f2 is output from the flip-flop 4.
It is input to terminal D of No. 11. As a result, flip-flop 411 has buffers 306 and 413,
Also, the clock signal a1 inputted to the terminal CK via the inverter 415 enters the set state, and the output signal g2 outputted from the terminal Q is set to a logic value of 1.
and output signal h2 output from the terminal.
Set to logical value 0. On the other hand, clock switching circuit 4
In this case, the flip-flop 401 is brought into a reset state by the clock signal a2 inputted to the terminal CK via the inverter 403, and the output signal c2 outputted from the terminal Q is set to a logical value of 0. The output signal c2 is connected to the terminal D of the flip-flop 409,
and input to terminal D of flip-flop 310 via buffers 412 and 314, respectively. The flip-flop 409 is connected to the inverter 40
Clock signal a input to terminal CK via 3
2, it enters a reset state and sets the output signal e2 output from the terminal Q to a logical value of 0. Flip-flop 310 also has buffers 406 and 3
Clock signal a2 input to CK via 18
This causes a reset state, and the output signal f1 output from the terminal Q is set to a logical value of 0. The output signal f1 is input to the terminal D of the flip-flop 311. As a result, flip-flop 311 connects buffers 406 and 313 and inverter 3
It is reset by the clock signal a2 applied to the terminal CK via the terminal CK, and the output signal g1 outputted from the terminal Q is set to a logic value 0, and the output signal h1 outputted from the terminal is set to a logic value 1. As a result, in the clock switching circuit 3, the clock signal a1 is connected to the gates 304 and 3 which are in the conductive state.
05 as an output clock signal d1, and in the clock switching circuit 4, the clock signal a1 is also output as an output clock signal d2 via buffers 306 and 413 and gates 407 and 405 which are in a conductive state. . In this state, when the switching signal b1 changes to a logic value of 0 and the switching signal b2 changes to a logic value of 1 at time t1, the flip-flop 301 enters a reset state at time t2, changing the output signal c1 to a logic value of 0. As a result, the flip-flop 410 at time t
3, and the output signal f2 is changed to a logical value of 0. Flip-flops 309 and 411, which receive the output signal c1 or f2 having a logic value of 0, are reset at time t4 and change the output signals e1 and g2 to logic 0, respectively. As a result, gates 304 and 407 become blocked and stop outputting clock signal a1 as output clock signals d1 and d2. Furthermore, the output signal h2 outputted from the terminal of the flip-flop 411 which is in the reset state is changed to a logic value of 1, so that the gate 402 becomes conductive, and the switching signal b2 is inputted to the terminal D of the flip-flop 401. As a result, flip-flop 4
01 is set to the set state at time t5 by the clock signal a2 inputted to the terminal CK via the inverter 403, and changes the output signal c2 to a logical value of 1. The output signal c2 is sent to the flip-flop 3 in the clock switching circuit 3 via the terminal D of the flip-flop 409 and the buffers 412 and 314.
The signals are input to terminals D of 10, respectively. As a result, flip-flop 310 is set to a set state at time t6 by clock signal a2 inputted to terminal CK via buffers 406 and 313, and sets output signal f1 outputted from terminal Q to a logical value 1. The output signal f1 is output from the flip-flop 311.
is input to terminal D of The flip-flop 409 receives the output signal c2, which has a logical value of 1, as follows.
The clock signal a2 inputted to the terminal CK via the inverter 403 brings it into the set state at time t7, sets the output signal e2 output from the terminal Q to a logic value of 1, and the output signal f1 which has become a logic value of 1.
The flip-flop 311 inputted with
Clock signal a2 supplied to terminal CK via
As a result, a set state is entered at time t7, and the output signal g1 output from the terminal Q is set to a logic value 1, and the output signal h1 output from the terminal is set to a logic value 0. As a result, gates 307 and 404 become conductive, and clock signal a2 is output as output clock signals d1 and d2.

As is clear from the above description, according to this embodiment, the clock signal a2 input to the gate 307 via the buffers 406 and 313 has a delay time with respect to the output signal g1 that controls the conduction state of the gate 307. Therefore, there is no possibility that an abnormal pulse will be generated at the time t7 when the clock signal a2 is outputted as the output clock signal d1.

Note that FIGS. 3 and 4 are only one embodiment of the present invention, and for example, the switching operation is performed when the output clock signal d1 that outputs the clock signal a1 is
(and d2) to the clock signal a2, and the output clock signal d2 (and d2) which is outputting the clock signal a2 is
The effects of the present invention do not change even when the clock signal a1 is switched from clock signal a1 to clock signal a1.

(f) Effects of the Invention As described above, according to the present invention, it is possible to prevent the generation of abnormal pulses when switching the clock signal in the dual system, thereby preventing malfunctions of the dual system. I can do it.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a conventional clock switching circuit, FIG. 2 is a diagram showing an example of the clock switching process in FIG. 1, and FIG. 3 is a diagram showing a clock switching circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing an example of the clock switching process in FIG. 3. In the figure, 1 and 2 are clock signal generation circuits, 3 and 4 are clock switching circuits, 301, 3
09,310,311,401,409,410
and 411 are flip-flops, 302, 30
4, 305, 307, 402, 404, 405 and 407 are gates, 303, 315, 403 and 415 are inverters, 306, 312, 31
3,314,316,317,406,412,
413, 414, 416 and 417 are buffers, a1 and a2 are clock signals, b1 and b2 are switching signals, c1, c2, e1, e2, f
1, f2, g1, g2, h1 and h2 are output signals, and d1 and d2 are output clock signals.

Claims (1)

[Claims] 1. In a dual system system each equipped with a clock signal generation circuit and a clock switching circuit, in which both systems simultaneously use the clock signal output from one of the clock signal generation circuits, the clock signal generation circuit in the own system A first flip-flop operates on the output own-system clock signal and holds a own-system switching signal that specifies a clock signal to be supplied to the own-system; a second flip-flop that holds an output signal; a first gate that controls supply of the own clock signal to the own system based on the output signal of the second flip-flop; and a clock signal generation circuit in the other system. a third flip-flop that operates on the output other system clock signal and holds an other system switching signal held in an other system clock switching circuit that designates a clock signal to be supplied to the other system system; and the other system clock signal. a fourth flip-flop that operates as a gate and holds the output signal of the third flip-flop; and a second gate that controls supply of the external clock signal to the own system based on the output signal of the fourth flip-flop. , and a third gate for controlling input of the self-system switching signal to the first flip-flop based on the output signal of the fourth flip-flop.