JPS5994123A - Clock switching circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of an abnormal pulse at switching, by allowing a clock signal to have no delay time for a signal which controls the conduction state of an output gate when the output clock signal is switched from the clock signal of one system to that of the other. CONSTITUTION:Clock switching circuits 3 and 4 select simultaneously one of a clock signal a1 outputted from a clock signal generating circuit 1 and a clock signal a2 outputted from a clock signal generating circuit 2 on a basis of designation of inputted switching signals b1 and b2 and supply the selected signal as output clock signals d1 and d2 into their own systems. In this case, since the signal a2 inputted to a gate 307 through a buffer 406 and a buffer 313 has no delay time for a signal g1 which controls the conduction state of the gate 307, an abnormal pulse is not generated at the time when the signal a2 is outputted as the output signal d1. Similarly, an abnormal pulse is not generated when the output clock signal d1 is switched to the signal a1.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention comprises a clock switching circuit, particularly a clock signal generation circuit and a clock switching circuit. This article relates to a clock switching circuit in a dual system that is used in both systems at the same time.

(bl) Prior Art and Problems Fig. 1 is a diagram showing an example of a conventional clock switching circuit of this type, and Fig. 2 is a diagram showing an example of the clock switching process in Fig. 1. In Fig. 1, The clock signal generation circuit 1 and the clock switching circuit 3 belong to one system in the dual system, and the clock signal generation circuit 2 and the clock switching circuit 4 belong to the other system.The clock switching circuits 3 and 4 belong to the other system. , respectively input switching signal b
Based on the designation of 1 or b2, the clock signal generation circuit 1
Either one of the clock signal al outputted from the clock signal generation circuit 2 and the clock signal a2 outputted from the clock signal generation circuit 2 is simultaneously selected and supplied to each system as an output clock signal d1 or d2. The clock switching circuit 3 supplies the clock signal a1 outputted from the clock signal generation circuit 1 in the own system to the own system as an output clock signal d1 when the input switching signal bi does not have a logical value of 1,
Further, when the switching signal b1 indicates the logical value O, the clock signal a2 outputted from the clock signal generation circuit 2 in the other system is supplied to the own system as the output clock signal di. Similarly, the clock switching circuit 4 also outputs the clock signal a2 or al according to the logical value indicated by the switching signal b2.
It is supplied within the own system as 2. In FIG. 2, if the switching signal b1 is set to a logic value of 1 and the switching signal b2 is set to a logic value of 0, the switching signal b1 is passed through the gate 3o2 which is in a conductive state in the clock switching circuit 3. is input to the terminal of flip-flop 301. The flip-flop 301 is connected to the terminal CK via an inverter 303.
The clock signal a1 input to the terminal Q enters the cent state, and the output signal c1 output from the terminal Q is set to a logic value of 1. The output signal CI makes gate 304 conductive, gate 402 in clock switching circuit 4 blocked, and gate +-4o7 conductive. As a result, in the clock switching circuit 3, the clock signal a1 is transferred to the gate 30.
4 and 305 as the output clock signal d1, and in the clock switching circuit 4, the clock signal a1, which is supplied from the clock switching circuit 3 via the buffer 306, is supplied via the gates 407 and 405. and is supplied within its own system as an output clock signal d2.

As a result, the flip-flop 401 in the lock switching circuit 4 enters a reset state and outputs an output signal c2 with a logic value of O, and as a result, the gate 307 in the clock switching circuit 3 and the gate 404 in the clock switching circuit 4 enter a blocking state.
Clock signal a2 is never output as output clock signals d1 and d2. In this state, when the switching signal b1 changes to a logic value O and the switching signal b2 changes to a logic value 1 at time t1, the flip-flop 301 becomes a reset state at a time t2, changing the output signal C1 to a logic value 0. As a result, the gates 1-304 and 407 are in a blocked state, and the output clock signal d1 of the clock signal a1 is
and stops outputting as d2. Also, the output signal CI
As a result, the gate 402 in the clock switching circuit 4 becomes conductive, and the switching signal b2 is input to the terminal of the flip-flop 401. As a result, the flip-flop 401 is connected to the terminal C via the inverter 403.
The clock signal a2 inputted to K causes it to enter the cent state at time t3, changing the output signal C2 to a logical value of 1. As a result, gates 307 and 404 become conductive, and clock signal a2 is output as output clock signals d1 and d2.

In the lock switching circuit 4, the clock signal a2
is directly transmitted to the gate 404, so the output signal C2
When is set to logical value 1, clock signal a2 has already changed to logical value 0, and after time t4, normal clock signal a2 is output as output clock signal d2.
In the clock switching circuit 3, since the clock signal a2 is transmitted to the gate 306 via the buffer 406, a delay time occurs, and after the output signal c2 is set to a logic value of 1, the clock signal a2 is transmitted to the gate 306 via the buffer 406. As a result, an abnormal pulse is output as the output clock signal d1 from time t3 to t3', causing various malfunctions within the own system.

As is clear from the above explanation, in a conventional clock switching circuit, the output clock signal d1 is changed to the clock signal a.
When switching from clock signal a2 to clock signal a2, buffer 4
An abnormal pulse based on the delay time of the clock signal a2 passing through the output clock signal d1 is outputted as the output clock signal d1, and there is a risk of causing a malfunction in the own system.

(C1 Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional clock switching circuit as described above, and to provide a means for preventing the generation of abnormal pulses that cause system malfunction during switching. .

(d+ Structure of the Invention) This object is to provide automatic control in a dual-system system, each of which is equipped with a clock signal generation circuit and a clock switching circuit, and in which both systems simultaneously use the clock signal output from one of the clock signal generation circuits. a first flip-flop that operates with a local clock signal output from a clock signal generation circuit in the system and holds a local switching signal that specifies a clock signal to be supplied to the local system; a second flip-flop that operates and holds the output signal of the first flip-flop; and a first flip-flop that controls supply of the home system clock signal to the home system based on the output signal of the second flip-flop. It operates with the gate and the other system clock signal output from the clock signal generation circuit in the other system, and holds the other system switching signal that specifies the clock signal to be supplied to the other system, which is held in the other system clock switching circuit. a third flip-flop that operates based on the other-system clock signal and holds the output signal of the third flip-flop; a second gate that controls the supply of the signal to the own system;
This is achieved by providing a third gate that controls input of the self-system switching signal to the first flip-flop based on the output signal of the fourth flip-flop.

(el　Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing a clock switching circuit according to an embodiment of the present invention, and FIG. 4 is a diagram showing an example of the clock switching process in FIG. 3. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 3, when the switching signal bl is set to a logic value of 1 and the switching signal b2 is set to a logic value of 0, the flip-flop 301 to which the switching signal b1 is input via the gate 302 to the inverter 303
The clock signal a1 inputted to the terminal CK via the terminal CK enters the cent state, and the output signal c1 outputted from the terminal Q is set to a logical value of 1. The output signal C1 is connected to terminal D of flip-flop 309 and buffers 312 and 414.
The flip-flop 41 in the clock switching circuit 4
Each signal is input to the 0 terminal. flip flop 3
09 enters the cent state by the clock signal al input to the terminal CK via the inverter 303, and sets the output signal e1 output from the terminal Q to a logical value of 1.

Furthermore, the flip-flop 410 receives a clock signal a1 input to the terminal CK via the buffers 306 and 413.
This results in a set state, and the output signal f2 output from the terminal Q is set to a logical value of 1.

The output signal f2 is input to the terminal of the flip-flop 411. As a result, the flip-flop 411 is set to a set state by the clock signal a1 inputted to the terminal CK via the buffers 306 and 413 and the inverter 415, sets the output signal g2 outputted from the terminal Q to a logic value 1, and The output signal h2 output from Q is set to a logical value of 0. On the other hand, in the clock switching circuit 4, the flip-flop 401 is brought into a reset state by the clock signal a2 inputted to the terminal CK via the inverter 403, and the output signal C2 outputted from the terminal Q is set to a logical value of 0. The output signal C2 is output from the flip-flop 40.
9 and the terminal D of flip-flop 310 via buffers 412 and 314, respectively. The flip-flop 409 is reset by the clock signal a2 input to the terminal CK via the inverter 403, and sets the output signal e2 output from the terminal Q to a logical value of 0. Furthermore, the flip-flop 310 is brought into a reset state by the clock signal a2 inputted to the terminal CK via the buffers 406 and 313, and
The output signal f1 outputted from the output signal f1 is set to a logical value of 0. The output signal f1 is input to the terminal of the 0 flip-flop 311.

As a result, flip-flop 311 connects terminal CK via buffers 406 and 313 and inverter 315 to terminal CK.
The clock signal a2 inputted into the terminal Q sets the output signal g1 to a logic value O, and sets the output signal h1 output from the terminal Q to a logic value 1. As a result, in the clock switching circuit 3, the gates 304 and 3 to which the clock signal a1 is in a conductive state are
05 as an output clock signal d1, and also in the clock switching circuit 4, the clock signal a1 is output as an output clock signal d2 via buffers 306 and 413 and gates 407 and 405 which are in a conductive state.
is output as In this state, at time tl, the switching signal b1 becomes the logic value O, and the switching signal b2 becomes the logic value 1.
, the flip-flop 301 enters the reset state at time t2 and changes the output signal C1 to a logic value O.

As a result, the flip-flop 410 enters the reset state at time t3 and changes the output signal f2 to a logical value of 0 (1). Flip-flops 309 and 411 to which the output signal cl or f2, which has a logic value of O, is input, are activated at time t.
4, the output signal e1 and g2 are changed to logical value O.

As a result, gates 304 and 407 become blocked,
The output of clock signal a1 as output clock signals d1 and d2 is stopped. Also, the output signal h output from the terminal Q of the flip-flop 411 which is in the reset state
2 is changed to the logical value 1, the gate 402 becomes conductive, and the switching signal b2 is transferred to the flip-flop 401.
input to the terminal. As a result, the flip-flop 401
enters the cent state at time t5 due to the clock signal a2 input to the terminal GK via the inverter 403, and changes the output signal C2 to a logic value of 1. The output signal C2 is connected to the terminal D1 of the flip-flop 409 and the buffer 412.
and 314 to the terminals of the flip-flop 310 in the clock switching circuit 3, respectively. As a result, flip-flop 310 has buffers 406 and 3
The clock signal a2 inputted to the terminal CK via 13 to 2 brings it into the cent state at time t6, and sets the output signal f1 outputted from the terminal Q to a logic value of 1. The output signal f1 is input to the terminal of the flip-flop 311. The flip-flop 40 receives the output signal C2, which has a logical value of 1.
9 enters the cent state at time t7 by the clock signal a2 input to the terminal CK via the inverter 403,
Set the output signal e2 output from the terminal Q to a logical value of 1,
Furthermore, the flip-flop 311 to which the output signal f1 having a logical value of 1 is input enters the cent state at time t7 due to the clock signal a2 supplied to the terminal GK via the buffers 406 and 313 and the inverter 315, and from the terminal Q The output signal g1 to be output is set to a logical value of 1, and the output signal h1 to be output from the terminal Q is set to a logical value of O.

As a result, gates 307 and 404 become conductive,
Clock signal a2 is output as output clock signals d1 and d2.

As is clear from the above description, according to the present embodiment, the gate 30 via the buffers 406 and 313
Since the clock signal a2 input to the gate 307 has no delay time with respect to the output signal g1 that controls the conduction state of the gate 307, an abnormal pulse is generated at the time t7 when the clock signal a2 is outputted as the output clock signal d1. There's no fear.

It should be noted that FIGS. 3 and 4 are only one embodiment of the present invention, and for example, the switching operation is performed when the output clock signal d1 (and d2), which is outputting the clock signal a1, is switched to the clock signal a2. is not limited to,
The effects of the present invention do not change even when switching the output clock signal d2 (and dl) outputted from the clock signal a2;tt to the clock signal a1.

(f) Effects of the invention According to the present invention, in the dual system,
It is possible to prevent the generation of abnormal pulses when switching clock signals, and it is possible to prevent malfunctions of the dual system.

[Brief explanation of drawings]

4. FIG. 1 is a diagram showing an example of a conventional clock switching circuit, FIG. 2 is a diagram showing an example of the clock switching process in FIG. 1, and FIG. 3 is a diagram showing a clock switching circuit according to an embodiment of the present invention. , FIG. 4 is a diagram showing an example of the clock switching process in FIG. 3. In the figure, 1 and 2 are clock signal generation circuits, 3 and 4 are clock switching circuits, 301.309.310.
311.401.409.410 and 411 are flip-flops, 302.304.305.307.402
．． 404.405 and 407 are gates, 303.3
15.403 and 415 are inverters, 306.31
2.313.314.316.317.406.412
．． 413.414.416 and 417 are buffers, a
l and a2 are clock signals, bl and b2 are switching signals, cl, c2, el, e2, fl, f2, gl, g2
, hl and h2 are output signals, and dl and d2 are output clock signals. 5 Figure 1 3 t4 Figure 2 Figure 3

Claims (1)

[Claims] In a dual-system system where each system is equipped with a clock signal generation circuit and a clock switching circuit, and both systems simultaneously use the clock signal output from one of the clock signal generation circuits, the output from the clock signal generation circuit within the own system. a first flip-flop that operates with the own system clock signal and holds a own system switching signal that specifies a clock signal to be supplied to the own system; a second flip-flop that holds an output signal of the second flip-flop, a first gate that controls the supply of the local clock signal to the local system based on the output signal of the second flip-flop, and a clock signal in the other system. a third flip-flop that operates with the other system clock signal output from the generation circuit and holds an other system switching signal held in the other system clock switching circuit that designates the clock signal to be supplied to the other system system; A fourth flip-flop operates on the other-system clock signal and holds the output signal of the third flip-flop, and supplies the other-system clock signal to the own system by the output signal of the fourth flip-flop. Clock switching characterized by providing a second gate for controlling, and a third gate for controlling input of the self-system switching signal to the first flip-flop based on the output signal of the fourth flip-flop. circuit.