JPS63250211A - Signal detecting circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction by inputting two signals of an inverting signal obtained by delaying and inverting an input signal and a delaying signal obtained by delaying the input signal to an OR circuit and obtaining an output from the OR circuit. CONSTITUTION:An input NOR4 directly connects one input to an input terminal 1, connects one other input through a delaying circuit 9 to the input terminal 1, connects one remaining input through a delaying circuit 6 and an NOR 7 into the input terminal and the output is connected through a first output terminal 2 and an inverter 5 to a second output terminal 3. An input signal, an inverting signal obtained by delaying and inverting the input signal, a delaying signal obtained by delaying the input signal are inputted to an OR circuit and the input signal of the pulse width of a constant time width or above is selected and outputted from the OR circuit. Consequently, when the input signal having the pulse width of a certain constant time width or above is not obtained, it cannot be detected as a signal. Thus, malfunction can be prevented to an impulse noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal detection circuit, and particularly to a signal detection circuit that detects an input signal having a certain time width or more.

[Conventional technology]

Conventionally, as this type of signal detection circuit, there has been one shown in FIG. 7 or FIG. 9, for example.

Basically, two inputs of No. 34 and 44 are connected to input terminals 31 and 41, and the other input is connected from the input terminal to the serial sister circuits 36 and 47 and the No. 37 deaf circuit for signal inversion. It is connected via an inverter 47. In the circuit shown in Fig. 7, No. 37, No. 38 are connected to each other to form a clip flop, and the output from the first output terminal 32 is fed back to this clip flop. . In both the circuits of FIGS. 7 and 9, the output is taken directly from the N0Rs 34,44. It has a first output terminal and a second output terminal 33.43 which is taken out as an inverted output via an inverter 35.45 (5).

Next, the operation of the circuit shown in FIG. 7 will be explained. To simplify the explanation, it is assumed that the delay time of the delay circuit 36 is sufficiently larger than the delay time of one stage of gates.

First, consider the case where a signal having a time width longer than the delay time of the input terminal 311C delay circuit 36 is input as shown in FIG. 8(a). When the input signal is in the 71-i state, that is, the input terminal 31 is in the high state, the two-man power output is 34.37
and the output of the delay circuit 36 is in the open state, 2 inputs N0
The output of R38 is high. When the input signal changes from a high state to a low state, the output of the two-input NOR34, that is, the output terminal 32, changes from a low state to a high state, and the output of the two-input N0R38 changes from a high state to a low state, and the two-input NOR34 changes from a high state to a low state.
The output of the OR37 changes from the low state to the high state, and this output is delayed through the delay circuit 36 and input to the two-input N0R34, which outputs the output of the two-power NOR34, that is, the output terminal 3.
2 changes sequentially to the low state again. Therefore, a high state corresponding to the delay time of the delay circuit 36 is obtained at the first output terminal 32.

Ninth, when the input signal changes from low state to high state,
The blade of the two-man NOR34 remains raw.

The output of the two-man power NOR 37 changes from a high state to a low state, the output of the two-man power NOR 38 changes from a low state to a high state, and the output of the two-man power NOR 37 goes to the delay circuit 36f! : input to the two-man power NOR 34 with a delay.

Next, consider the case where a signal with a pulse width shorter than the delay time of the delay circuit 36 is input to the input terminal 31 as shown in FIG. Yes, when the input signal changes from a high state to a low state, the output of the two-input NOR34, that is, the first output terminal 32, changes from a low state to a high state, and the two-input NOR38
output from high state to low state, facing down 2 inputs N0R3
The output of No. 7 changes from a low state to a high state. When the t1 human power signal changes from low state to high state, 3 human power NOR
34, the first output terminal 32 changes from a high state to a low state, the output of the two-man power NOR 37 changes from a high state to a low state], and the output of the two-man power NOR 38 changes from a low state to a high state. The output of the delay circuit 36 changes from a low state to a high state and then from a high state to a low state after a delay time has passed.

Therefore, an inverted signal of the input signal is obtained at the first output terminal 32.

In this way, a signal with a pulse width of a certain time or less is outputted to the first output terminal 32 in response to an input signal having an arbitrary pulse width, and the input signal can be detected. Sincerely, 2nd
The output terminal 33 of the first output terminal 320 can obtain an inverted output by the inverter 35.

Next, the operation of the circuit shown in FIG. 9 will be explained.

To explain the operation, as described above, the delay circuit 46
The delay time is set to a value sufficiently larger than the delay time of one stage of gates.

As shown in FIG. 10 (al), consider the case where a ratio signal is input to the input terminal 41 for a time longer than the delay time of the delay circuit 46. When the input signal is in a high state, two inputs N
0R44 is in a low state, the delay circuit 46 is in a high state, and the output of the inverter 47 is in a low state. When the input signal changes from a high state to a low state, the output of the two-input N0R44, that is, the first output terminal 42 changes from a low state to a high state, and the input signal is delayed through the delay circuit wr46, and changes from a high state to a low state. state, the output of the inverter 47 changes from a low state to a high state, and the output of the 2-input N0R44, that is, the first
The output terminal 42 of the output terminal 42 changes from the a state to the low state again.

Therefore, a state corresponding to the delay time of the delay circuit 46 is obtained at the first output terminal 42. Just to be sure, the input signal changes from low to high. ! -%2 human power N0R4
4 remains in the low state, the input signal is delayed through the delay circuit 46, and the inverter 47 changes from the low state to the high state.
The output of goes from high to low.

Next, consider the case where a signal having a pulse width shorter than the delay time of the input terminal 411C delay circuit 46 is input as shown in FIG. 10(b). When the input signal is in the high state, it is the same as described above. When the input signal changes from a high state to a low state, the output of the two-input NOR44, that is, the first output terminal 42 changes from a low state to a high state), and when the input signal changes from a low state to a high state, the output of the two-input NOR44 changes from a low state to a high state.
The output of , that is, the first output terminal 42 changes from a high state to a low state. At the output of the delay circuit 46, the same phase as the input signal appears after a delay time, and its inverted output becomes the output of the inverter 47.

In this way, a signal with a pulse width of a certain time or less is output to the first output terminal 42 for a nine-power signal having an arbitrary pulse @, and the input signal can be detected. By the way, the second output terminal 43 can be inverted from the first output terminal 42 by using the inverter 45.

[Problem that the invention seeks to solve]

The conventional signal detection circuit described above outputs a signal with a pulse width of a certain time or less in response to an input signal having an arbitrary pulse width, and can detect the input signal.

However, it detects signals even if the pulse width of the input signal is small, and it also operates against impulse noise, which has the disadvantage of detecting noise as an input signal and causing the entire system to malfunction. there were.

[Means for solving problems]

The signal detection circuit of the present invention is a signal detection circuit that detects an input signal having a pulse width of a certain time width or more. The delayed signal obtained by the delay is input to an OR circuit, and an input signal having a pulse width of a certain time width or more is selectively outputted from the OR circuit.

In other words, while conventional signal detection circuits detect even impulse-like noise as a signal in order to be able to detect input signals with a small pulse width, the present invention detects impulse-like noise as a signal. Since an input signal that does not have a pulse width cannot be detected as a signal, malfunctions can be prevented due to impulse noise.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a signal detection circuit according to a first embodiment of the present invention. In the figure, the three-power N0R4 has one input connected directly to the input terminal 1, another input connected to the input terminal l via the delay circuit 9, and one input of the remaining input connected to the delay circuit 6.
and N0R7, and the output is connected to the first output terminal 2 and the second output terminal 3 via the inverter 5.

Next, the operation will be explained. To simplify the explanation, the delay times of the delay circuits 6 and 9 are assumed to be sufficiently larger than the delay time of one gate stage.

First, consider the case where a signal having a time width longer than the delay time of the delay circuit 9 is input to the input terminal 1 as shown in FIG. 2(a). When the input signal is in a high state, that is, when the input terminal l is in a high state, the outputs of the three-man power N0R4, the two-man power N0R7 and the delay circuit 6 are in a low state, and the two-man power N0R8
and the output of the delay circuit 9 is in a high state. When the input signal changes from a high state to a low state, the output of the delay circuit 9 reaches the delay time and changes from a high state to a low state.
The output of oR4, that is, the output terminal 2 changes from a low state to a high state, the output of two-man power N0R8 changes from a high state to a low state, the output of two-man power No. 7 changes from a low state to a high state, and this output changes from a low state to a high state. Delayed through, 3 manpower NO
Input to R, 4, 3-man power NOR.

4, that is, output terminal 2, sequentially changes to the low state again. Therefore, a high state corresponding to the delay time of the delay circuit 6 is obtained at the first output terminal 2.

Also, when the input signal changes from low state to high state,
The output of the 3-man power N0R4 remains high, and the 2-man power N0R
7's output changes from high state to low state, 2-man power N0R
8 output changes from low state to high state), two-man power N0R
The output of 7 is delayed through the delay circuit 6 and the 3-man power N0R4
-10,000, the input signal is delayed through all the delay circuits 9 and input to the three-way input N0R4.

Next, consider the case where a signal having a pulse width shorter than the delay time of the delay circuit 9 is input to the input terminal 1 as shown in FIG. 2(b). When the input signal is in the high state, it is the same as described above. When an input signal with a short pulse width is input to the input terminal 1, the delay time of the delay circuit 9 is longer than the pulse width, so the input signal and the output of the delay circuit 9 do not become low at the same time, so the output of the three-man powered NoR4 That is, the first output terminal 2 maintains the lower state. In a hurry, two-man power No.
The output of R8 is held in a high state, and the outputs of the two-way input N0R7 and the delay circuit 6 are held in a low state.

In this way, only when an input signal with a pulse width of a certain time width or more is input to the input terminal 1, the output terminal 2 receives the input signal.
Can detect input signals. Further, the second output terminal 3 can obtain an inverted output of the first output terminal 2 by the inverter 5.

〔Example〕

Next, a second embodiment of the present invention will be described.

FIG. 3 shows a signal detection circuit according to a second embodiment of the present invention. In the figure, the three-man power NOR 14 has one input connected directly to the input terminal 11, the other input connected to the input terminal via the delay circuit 18, and the remaining input connected to the inverter 1.
7 and a delay circuit 16, an input connection is made to which a delay circuit 18 is connected. When explaining the operation,
As before, the delay time of delay circuits 16 and 18 is
The value should be sufficiently large compared to the delay time of the stage.

As shown in FIG. 4(a), the delay circuit 1 is connected to the input terminal 11.
If you input a signal with a time width longer than the delay time of 8, it will be difficult. When the input signal is in a high state, delay circuit 1
The outputs of 6 and 18 are high, and the output of inverter 17 and 3
The output of human power N0RI 4 is in a low state. When the input signal changes from the 1 state to the low state, the output of the delay circuit 18 reaches the delay time and changes from the high state to the low state.
The output of the three-man power NOR 14, that is, the first output terminal 12 changes from a low state to a high state. The output of the delay circuit 18 is delayed via the delay circuit 16 and changes from a high state to a low state), the output of the inverter 17 changes from a low state to a high state, and the output of the three-man power NoR 14 becomes a low state again. Therefore, a high state corresponding to the delay time of the delay circuit 16 is obtained at the first output terminal 12. Further, when the input signal changes from the low state to the high state, the output of the delay circuit 18 reaches the delay time and changes from the low state to the high state.
This output signal is delayed through the delay circuit 16 and changes from a state to a high state, the output of the inverter 17 changes from a high state to a low state, and the output of the three-man power NOR 14 maintains a low state.

Next, consider the case where a signal having a pulse width shorter than the delay time of the delay circuit 18 is input to the input terminal 11, as shown in FIG. 4(b). When the input signal is in the high state, it is the same as described above. When an input signal with a short pulse width is input to the input terminal 11, the delay time of the delay circuit 18 is longer than the pulse width, so the input signal and the output of the delay circuit 18 do not become low at the same time, so the output of the three-man power NOR 14 That is, the first output terminal 12 maintains the rotor state. The output of the delay circuit 18 is delayed through the delay circuit 16, inverted by the inverter 17vc, and becomes the input of the three-power NOR 14.

In this way, an input signal can be detected at the first output terminal 12 only when an input signal with a pulse width longer than a certain period of time is input to the input terminal 11. Further, the second output terminal 13 can obtain an inverted output of the output terminal 2 by the inverter 15.

FIG. 5 shows a signal detection circuit according to a third embodiment of the present invention.

In the figure, the three-man power NOR 24 has one input connected directly to the input terminal 21, another input connected to the input terminal 21 via the delay circuit 28, and the remaining input connected to the inverter 27 and the delay circuit 26. ◎Here, if the delay time of the delay circuit 26 is made longer than the delay time of the delay circuit 28, the operation is exactly the same as that shown in FIG. 3 of the second embodiment. be. The only difference is that a high state is obtained at the first output terminal 22 by the delay time difference between the delay circuit 26 and the delay time 28, but this delay time difference is
By making the delay time equal to the delay time of the delay circuit 16 shown in the figure, as shown in FIG.
The third embodiment provides results completely equivalent to those of the second embodiment.

〔Effect of the invention〕

As explained above, the present invention provides an input signal, an inverted signal obtained by delaying and inverting this input signal, and an input signal ft.
By inputting the two delayed signals obtained by delaying into a t-logic logic circuit and obtaining an output from this logic sum circuit, short pulse widths such as impulse-like noise of less than a certain time width can be detected. It has the effect of not detecting hazards and preventing malfunctions.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 (
al, (bl is a waveform diagram explaining the operation of the circuit in FIG. 1, FIG. 3 is a circuit diagram showing the second example of the non-invention 11, and FIGS. 4(a) and (b) are FIG. 2. FIG. 5 is a circuit diagram showing a third embodiment of the present invention,
6(al), (b) are waveform diagrams explaining the entire operation of the circuit in FIG. 5, FIG. 7 is a circuit diagram showing the conventional signal detection port PI&, and FIG. FIG. 9 is a circuit diagram showing another conventional signal detection circuit, and FIG. 10 (al, (bl) is a waveform diagram explaining the operation of the circuit in FIG. 9. 1.11, 21, 31, 41... Input terminal, 2
゜12.22, 32, 42...First output terminal, 3゜13.23, 33.43... Second output terminal, 4゜14.24-... -3 human power NOR, 7, 8
,34,37゜38.44...2-person power NOR,
5, 15, 17° 25.27, 35, 45.47...
...Inverter, 6.9, 16, 18, 26, 28,
36.46...Delay circuit. ZunuriJ Road No. 3 Concave and sunken circuit grass 5 times sheep 2 Concave rod 4I11 Rod zWJ grass 7 Figure 7

Claims (1)

[Claims] In a signal detection circuit that detects an input signal having a pulse width of a certain time width or more, delaying the input signal and the input signal,
A signal detection circuit characterized in that an inverted signal obtained by inverting the input signal and a delayed signal obtained by delaying the input signal are input to an OR circuit.