JPH049676Y2 - - Google Patents

Description

[Detailed description of the invention] (Technical field of the invention) The invention counts a fixed number of normal pulses and abnormal pulses each generated at a predetermined period corresponding to the logical value of a binary status signal, and This relates to a status determination circuit that determines normality or abnormality based on the results.

(Prior art) A conventional status determination circuit that determines normality or abnormality based on two pulse trains, normality and abnormality, generated at a predetermined period in response to the logical values of a binary status signal (see Japanese Patent Publication No. 19118-1982) ) as the first
This will be explained using figures. In the figure, 21 and 31 are pulse multipliers, 22, 23, 32, and 33 are AND gates, 23 and 34 are OR gates, 25 and 35 are inhibit gates, and 11 are counters 12 and 13.
is a detector, and 14 is an S-R flip-flop.

The abnormal pulse is applied to an AND gate 22 and also to an AND gate 23 through a pulse multiplier 21. The pulse multiplier 21 multiplies the number of input pulses by K times (K>1). The AND gates 22 and 23 are opened and closed by the normal output signal and the abnormal output signal Q of the S-R flip-flop 14, respectively, and send the abnormal pulse or a pulse K times the abnormal pulse to the counter 11 through the OR gate 24 and the inhibit gate 25. Give it to up terminal U.

A normal pulse is applied to an AND gate 32 and also to an AND gate 33 through a pulse multiplier 31. and gate 32,3
3 is opened and closed by the abnormal output signal Q and the normal output signal of the S-R flip-flop 14, respectively, and sends the normal pulse or a pulse K times the normal pulse to the down terminal D of the counter 11 through the OR gate 34 and the inhibit gate 35. give to The counter 11 is a so-called up-down counter that counts down normal pulses and counts up abnormal pulses. The count value M of the counter 11 is given to detectors 12 and 13, and it is detected whether the count value M has reached zero or a predetermined value _N1, respectively. The output signals of detectors 12 and 13 are applied to S-R flip-flop 14. S-R flip-flop 14 is reset by the front edge of the output signal of detector 12 and set by the front edge of the output signal of detector 13. The output signals of detectors 12 and 13 are also applied to inhibit gates 35 and 25, respectively. The Q output of the S-R flip-flop 14 is output as an abnormal output signal, and the output is output as a normal output signal.

The operation of the device configured in this way is as follows. The operation pattern is shown in FIG. 2 for the case of K=2. Initially, the normal state is established, the count value M of the counter 11 is between zero and _N1 , and S-
Assume that R flip-flop 14 has been reset. The S-R flip-flop 14 produces a normal output after being reset. At this time,
The AND gates 22 and 33 are open due to the normal output I, but the AND gates 23 and 32 are closed because the abnormal output Q is not generated. Since the count value M of the counter 11 is between zero and _N1 ,
Both inhibit gates 25 and 35 are open.

In this state, normally normal pulses are generated continuously, so these pulses are multiplied by K by the pulse multiplier 31 and applied to the down terminal D of the counter 11 through the AND gate 32, the OR gate 34, and the inhibit gate 35. Therefore, the count value M of the counter 11 decreases by K. If the status signal is temporarily reversed due to noise or the like, an abnormal pulse is generated, so this pulse is directly applied to the up terminal U of the counter 11 through the AND gate 22, OR gate 24, and inhibit gate 25. The number M is only set back by 1. As a result, the maintenance of the currently determined normal state is performed with K times the sensitivity of the operation to reverse it.

If the occurrence of an abnormal pulse is not due to a temporary reversal due to status signal noise, etc., but is due to a true abnormal condition, the frequency of occurrence of abnormal pulses is high, so this difference in sensitivity can be ignored. , the count value M of the counter 11 increases by one. Since the S-R flip-flop 14 is not set until the count value M reaches the predetermined value _N1 , it continues to generate a normal output signal, and a hysteresis corresponding to _N1 is applied to confirm an abnormal state. I will have it. Eventually, the count value M of the counter 11 reaches a predetermined value _N1 . Then, the detector 13 detects this and sets the S-R flip-flop 14 to generate an abnormal output signal, thereby confirming the abnormal state.

When an abnormal state is established, the open/close states of the AND gates 22, 23, 32, and 33 are alternated, and an abnormal pulse is output to the up terminal U of the up/down counter 11 by the pulse multiplier 21.
The signal is multiplied and given, and the normal pulse is given to the down terminal D as it is. Therefore, the up-down counter 11 counts down one by one for each normal pulse, but counts up by K for each abnormal pulse.
The operation is the reverse of the above state.

FIG. 3 shows an example of the configuration of the pulse multipliers 21, 31, and their operation is shown in the time chart of FIG. In FIG. 3, 36 is a monostable multivibrator, 37 is a digital oscillator, and 38 is an OR gate. The pulse width of the abnormal or normal input pulse a is multiplied by the monostable multivibrator 36 and inputted to the AND gate 38 as b.
In addition, the other input of the AND gate 38 is
The output c of a digital oscillator 37 that generates a pulse train having a period shorter than that of at least abnormal pulses or normal pulses is added.
Therefore, the pulse train d appears at the output of the AND gate 38 only when the logic of the output b of the monostable multivibrator 36 is true, and a plurality of output pulses d are obtained by one input pulse a. In Figure 4, K
This is shown when =4.

In this way, the status is determined with emphasis on the currently established state, but the pulse multiplier poses a problem when considering converting the circuit into an LSI. This is because it is difficult to incorporate analog circuits into semi-custom LSIs (gate arrays) that are currently in widespread use. Therefore, it is better not to use monostable multivibrators, oscillators, etc. However, for the oscillator, it is possible to supply the clock signal from other circuits instead.

Moreover, this part is wasted because when one of the two circuits is used, the other is not.
Furthermore, if the generation period of abnormal or normal pulses becomes short, the period of the digital oscillator also becomes short, which is disadvantageous in that the oscillation frequency must be increased.

(Purpose of the invention) The present invention is particularly effective when considering LSI circuits in order to improve the conventional drawbacks as mentioned above, and can provide large hysteresis with a small amount of hardware and a simple configuration. The present invention provides a status determination circuit that is capable of responding to high-speed inputs.

(Structure and operation of the device) The present invention will be explained in detail below.

FIG. 5 shows an embodiment of the present invention. Components with the same numbers as in FIG. 1 are the same as or correspond to those in FIG. 1. Other than that, 41.4
2 is an AND gate, 43 is an OR gate, and 15 is a counter.

An abnormal pulse is applied to the AND gate 41, and a normal pulse is applied to the AND gate 42, which are opened and closed depending on a normal output signal and an abnormal output signal, respectively.When an abnormal state occurs, a normal pulse is applied, and when a normal state exists, an abnormal pulse is applied. is passed through the OR gate 43 to the counter 15.
is input to. The counter 15 is a counter with B1 stages.

Further, the abnormal pulse is also given to the AND gate 22, and by opening and closing the AND gates 22 and 23 with the abnormal output signal and normal output signal, respectively, it is passed through the OR gate 24 and the inhibit gate 25 to the up terminal U of the counter 11. A selection is made as to whether the input signal is an abnormal pulse or an output pulse of the counter 15. The output pulse of the counter 15 is a carry-out pulse that is output when the count value is 2 ^B1 -1. Here, let K=2 ^B1 .

Similarly, for normal pulses, by opening and closing the AND gates 32 and 33 with the abnormal output signal and the normal output signal, respectively, the signal input to the down terminal D of the counter 11 through the OR gate 34 and the inhibit gate 35 is output to the carry out of the counter 15. Select whether to use pulse or normal pulse. The rest of the configuration is similar to the circuit shown in FIG.

The advantages of the device configured as described above are as follows. The operating state is shown in FIG. In the figure, the number of stages B1 of the counter 15 is temporarily shown as two stages.

It is assumed that the normal state is initially established, the count value M of the counter 11 is between zero and _N2 , and the S-R flip-flop 14 has been reset. S-R flip-flop 14 produces a normal output signal upon reset. At this time, the AND gates 41, 23, 3
3 is open, but AND gates 42, 22, and 32 are closed because there is no abnormal output signal.
Since the count value M of the counter 11 is between zero and _N2 , both inhibit gates 25 and 35 are open. In this state, normally normal pulses are generated continuously, so these pulses are sent to AND gate 33, OR gate 34, and inhibit gate 3.
5 and directly to the down terminal D of the counter 11. Therefore, the count value M of the counter 11 decreases by one. Here, if the status signal is temporarily reversed due to noise or the like, an abnormal pulse is generated, and this pulse is input to the counter 15 through the AND gate 41 and the OR gate 43. As a result, the count value L of the counter 15 increases by 1, and when a carry-out signal is generated, it is applied to the up terminal U of the counter 11 for the first time through the AND gate 23, the OR gate 24, and the inhibit gate 25, and the counter 15 is reset. Then, the count value L returns to zero. That is, one up pulse is input for every K abnormal pulses, and the abnormal pulse is multiplied by 1/K and applied to the up terminal U of the counter 11. As a result, the maintenance of the currently determined normal state is performed with K times the sensitivity of the operation to reverse it.

When the occurrence of an abnormal pulse is not due to a temporary reversal but is due to a true abnormal state, the frequency of occurrence of the abnormal pulse is high, so the count value M of the counter 11 is It will increase. Since the S-R flip-flop 14 is not set until the count value M reaches the predetermined value N ₂ , it continues to generate a normal output signal, and when an abnormal state is determined, K×N ₂
(In the case of the example shown in FIG _. 6, the hysteresis is 4×N ₂ ).In order to obtain the same hysteresis as _the hysteresis N ₁ shown in FIG. The number of stages can also be reduced. Eventually, the count value M of the counter 11 reaches a predetermined value _N2 ,
Detector 13 detects this and sets S-R flip-flop 14 to generate an abnormal output signal and establish an abnormal condition.

When the abnormal condition is confirmed, AND gates 41, 2
3, 33 and the AND gates 42, 22, 32 are alternately opened and closed, and the up terminal U of the counter 11 is
The abnormal pulse is directly applied to the down terminal D, and the normal pulse multiplied by 1/K is applied to the down terminal D. Therefore, the counter 11 counts down once for every K normal pulses, but counts up one by one for each abnormal pulse.
An operation is performed in which the normal side and abnormal side of the above state are reversed.

According to the abnormal configuration, the pulse multiplier, which required two configurations in the conventional example in order to give priority to the currently determined state, can be reduced to one configuration, and the amount of hardware can be reduced and the multiplier By replacing it with a counter that divides the frequency by 1/K, there is no need for a clock other than the frequency at which abnormal or normal pulses occur.
Compatible with high-speed circuits with short pulse generation cycles,
Furthermore, the number of stages of the counter can be reduced, and the amount of hardware can be further reduced.

FIG. 7 shows another embodiment of the present invention. In the figure,
Items with the same numbers as in FIGS. 1 and 5 are the same as or correspond to those in FIGS. 1 and 5. Other than that, 16 and 17 are counters, 18 is an OR gate, and 9 is a counter reset signal.
And gate 41, 42, 22, 23, 32, 3
3, OR gate 43, 24, 34, counter 15
The configuration is exactly the same as that shown in FIG. The difference from FIG. 5 is that the outputs of OR gates 24 and 34 are input directly to counters 16 and 17, respectively, instead of being input to the up and down terminals of counter 11 through inhibit gates 25 and 35, respectively. , the counter 16 counts abnormal pulses, and when a predetermined value N is reached, the S-R flip-flop is set by a carry-out signal, and the counters 16 and 17 are reset by a counter reset signal 9 through an OR gate 18.
Reset. Counter 17 counts normal pulses, and when it reaches a predetermined value N, it resets the S-R flip-flop with a carry-out signal and also resets the counters 16 and 17 with a counter reset signal 9 through OR gate 18.
Reset.

The operation of the circuit configured in this way is as follows. The operating state is shown in FIG. In the figure, the number of stages of the counters 15, 16, and 17 is assumed to be two stages.

It is assumed that the normal state is initially established and the S-R flip-flop 14 has been reset.
S-R flip-flop 14 produces a normal output signal upon reset. At this time, AND gates 41, 23, and 33 are open, and AND gates 42, 22, and 32 are closed, as in the case of FIG. In this state, normal pulses are normally generated continuously, so these pulses are directly given to the counter 17 through the AND gate 33 and the OR gate 34, and each time a normal pulse is generated, the count value M ₂ of the counter 17 is Increase by "1". Here, when an abnormal pulse is generated due to the inversion of the status signal due to noise etc., this pulse is input to the counter 15 through the AND gate 41 and the OR gate 43, so the count value L of the counter 15 increases by "1". When K is reached, a carry-out signal is generated. This output is passed through an AND gate 23 and an OR gate 24 to a counter 16.
and the counter 15 is reset. Therefore, the abnormal pulse is multiplied by 1/K, and the currently established normal state is maintained with K times the sensitivity of the operation to reverse it.

When the occurrence of an abnormal pulse is due to a true abnormal state, the frequency of occurrence of the abnormal pulse is high, so the count value M1 of the counter 16 will eventually become larger than the count value _M1 of the counter 17 despite this difference in sensitivity. It reaches N before the numerical value _M2 , outputs a carry-out signal, sets the S-R flip-flop 14, and confirms the abnormal state, but until then, the normal output signal continues to be generated, and the abnormal state is determined. As in FIG. 5, the state determination has a hysteresis of K×N (4×4 in the example of FIG. 8). At this time, the carry-out output of the counter 16 becomes the counter reset signal 9 through the OR gate 18, which is sent to the counters 16 and 17.
Reset both. When an abnormal condition is confirmed,
As in FIG. 5, the operations for abnormal pulses and normal pulses are reversed, and the sensitivity for normal pulses is multiplied by 1/K.

The above configuration realizes the same functions as in FIG. 5 with the same amount of hardware.

(Effects of the invention) According to the two embodiments described above, in both cases, the circuit configuration does not use a monostable multivibrator or digital oscillator, which would be an obstacle when implementing LSI, and the circuit configuration can be realized in an already established state. By sharing the circuit part that gives a certain weight to the normal side and the abnormal side, it is possible to reduce the amount of hardware or
When converting to LSI, we have achieved a reduction in the number of gates.
This effect becomes more pronounced as the value of the weighting constant K increases.

Furthermore, when weighting, instead of increasing the input pulse by a factor of K, the other input pulse is multiplied by 1/K, thereby keeping the relative weighting the same while increasing the speed of the input pulse with a short generation period. It has the great advantage of being compatible with circuits.

As explained above, according to the present invention, in a determination circuit that counts a fixed number of normal pulses and abnormal pulses generated in conjunction with a binary status signal, and determines a normal state or an abnormal state based on the results,
In addition to reducing the number of counter stages, it is suitable for high speed with less hardware or fewer gates than before.
This has the effect of realizing a circuit suitable for LSI.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of a conventional circuit, Figure 2 is a time chart for explaining the operation of the circuit in Figure 1, and Figure 3 is a block diagram showing an example of the configuration of a pulse multiplier used in the conventional example of Figure 1. Figure 4 is a time chart for explaining the operation of the circuit in Figure 3, Figure 5 is a time chart for explaining the operation of the circuit in Figure 3.
The figure is a block diagram showing one embodiment of the present invention, FIG. 6 is a time chart for explaining the operation of the circuit of FIG. 5, and FIG. 7 is a block diagram showing another embodiment of the present invention.
FIG. 8 is a time chart for explaining the operation of the circuit shown in FIG. 9... Counter reset signal, 11, 15, 1
6, 17... Counter, 12, 13... Detector, 14... S-R flip-flop, 21,
31... Pulse multiplier, 22, 23, 3
2, 33, 41, 42...and gate, 24,
34, 43, 18... Or Gate, 25, 35...
...inhibit gate, 36...monostable multivibrator, 37...digital oscillator, 38...
AND gate, a... Abnormal or normal input pulse, b... Monostable multivibrator output, c...
...Digital oscillator output, d...Pulse multiplier output.

Claims (1)

[Claims for Utility Model Registration] (1) A first selection means for selecting one of a normal pulse and an abnormal pulse corresponding to each binary status, and a normal pulse or an abnormal pulse selected by the selection means is predetermined. a frequency dividing means for dividing the frequency at a predetermined frequency division ratio; and a counting means for outputting an abnormal state output and a normal state output according to a counting result indicating which of the two input pulses reaches a predetermined count value. , a flip-flop that is set when the counting means outputs the abnormal state output, and outputs an abnormal output indicating an abnormal state, and is reset when the counting means outputs the normal state output, and outputs a normal output indicating a normal state; control means for causing the selection means to select the abnormal pulse according to the normal output; and control means for causing the selection means to select the normal pulse according to the abnormal output; and second selection means for causing the counting means to count the normal pulses and the abnormal pulses when the abnormal output is output, and for causing the counting means to count the output pulses of the frequency dividing means and the abnormal pulses, - A status determination circuit configured to extract abnormal output and normal output from the flop as a determination result. (2) The counting means uses the abnormal pulse or the abnormal frequency-divided pulse obtained by dividing the abnormal pulse by the frequency dividing means as an up input pulse, and the normal pulse or the normal pulse is frequency-divided by the frequency dividing means. an up-down counter with a normal pulse as a down input and a scale corresponding to the predetermined count value, and a set input to the flip-flop when the output of the up-down counter reaches the predetermined count value. 1st
and a second detector that outputs a reset input to the flip-flop when the output of the up-down counter does not reach the predetermined count value. status determination circuit. (3) The counting means counts the abnormal pulse or the abnormal frequency-divided pulse obtained by dividing the abnormal pulse by the frequency dividing means, and sets the flip-flop in the flip-flop when the count reaches a first predetermined count value. a first counter to which an input is applied, and a counter that counts the normal pulse or a normal frequency-divided pulse obtained by dividing the normal pulse by the frequency dividing means, and when a second predetermined count value is reached, the flip-flop a second counter to which a reset input is applied; and reset means to reset the first counter and the second counter when the set input or the reset input occurs. The status determination circuit according to the first item in the range.