JPS5981953A - Noise preventing circuit - Google Patents

Abstract

PURPOSE:To prevent noise with different in pulse width and to make advantageously a complex circuit constitution into IC formation by providing plural delay circuits different in delay time in an integrated circuit and selecting one of their outputs. CONSTITUTION:The delay circuits 21-2n having different delay times are provided and one of their outputs is selected by a selecting circuit 4 according to a control signal 5 and inputted to a deciding circuit 3 together with a direct input IN signal. The circuit 4 selects a delay circuit which prevents a noise sufficiently according to a normal signal and the pulse width of the noise. Namely, a delay time (t2''-t1'') is made shorter than the pulse width of the normal input signal and longer than the pulse width of the noise, so that the noise does not appear in a signal OUT since the signal IN is 0 at time t2''. Further, the delay time is shorter than the pulse width of the normal input signal and signals IN and DELAY are both 1 at time t5'', so the signal OUT is 1 continuously up to time t6'', so that the normal signal is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise prevention circuit that prevents malfunctions due to noise input in an integrated circuit.

In integrated circuits, is it a noise input or a normal input signal? It has been conventional practice to provide an internal circuit with a circuit that makes a judgment and outputs only normal input signals that should be detected. 1st
The figure shows a conventional circuit. Direct signal from input terminal 1,
and a determination circuit 3 which inputs both signals delayed through a delay circuit 2, determines whether the signal is a normal signal or noise, and blocks the passage of the noise. This circuit works by blocking all noise signals that do not have normal pulse widths. In the timing chart of FIG. 2, the input signal (IN) at time 11 is a noise signal, and the signal at time t4 is a normal signal. Output number 100 from delay circuit 2 (JJELA
Y) is (tz-tt) time and (ts-
t< ) It will take some time. Since the delay time of the delay circuit 2 is constant, both are equal. The determination circuit 3 operates as follows: 1) When both the ELAY signal and the iN signal become 1'', the output signal (OUT) of the determination circuit 3 changes from 0'' to '1'' and remains at '1'', and then 1. ) When both the ELAY signal and the IN signal become ``O'', the OUT signal changes from ``1'' to 0'' and maintains θ'', which can be realized by an RS flip 70 tube and a logic circuit. Therefore, in the second case where the pulse width of the noise signal is shorter than the delay time, the O[JT signal is not output when the IN signal is noise, and only the normal signal is output with a delay of the delay time. However, this noise prevention circuit does not work effectively unless the pulse width of the noise signal is shorter than the delay time. In other words, in the timing chart of FIG. 3, since the pulse width of the noise signal is longer than the delay time (h'-tt'), the noise signal also becomes the IN signal, DEI, and AY times the signal 1'', and as shown in the figure (0 [Output as a JT signal.

As explained above, in the conventional circuit, the pulse width determined as noise was fixed at a certain value, and the delay time of the delay circuit was fixed at a constant value.
This has the drawback that systems in which noise with a pulse width wider than a predetermined value may be input may malfunction by determining the noise as a normal input signal.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a circuit that can effectively block noise depending on a normal input signal and the pulse width of the noise.

The noise prevention circuit according to the present invention includes a plurality of delay circuits that delay all input signals from input terminals, a selection circuit that selects one of the outputs of the delay circuits, and a selection circuit that delays the output signal of the selection circuit and the input terminal. The present invention is characterized in that it is provided with a determination circuit which receives an input signal and blocks the passage of the input signal when the input signal at the input terminal is noise.

The invention will be explained in detail below with reference to the drawings.

FIG. 4 shows an embodiment of the present invention. In FIG. 4, a plurality of delay circuits 2□ to 2n each having a different delay time are shown.
A selection circuit 4 is provided for selecting and outputting any one of the outputs based on the control signal 5Vc. The direct large signal and the output signal of the selection circuit 4 are input to the determination circuit 3 .

Which of the outputs of the delay circuits 21 to 2n is selected is determined based on the pulse width of the normal signal and the noise, and a circuit sufficient to prevent noise is selected.

Now, if the IN signal is the same as shown in Figure 3, the delay time (h"-tl") is shorter than the pulse width of the normal input signal, and the noise pulse width is V as shown in Figure 5. By selecting a sufficiently long time, the IN signal is 0" at time t2vc, so no noise is output as the OUT signal. Also, at time t, the delay time is shorter than the normal input signal pulse width, so the IN signal is output.

1) Since both the ELAY signals are 1", the OUT signal becomes '1' at time 1, and until // ''1'1 time t6
“, it becomes “0” and a normal signal is output.

Next, another embodiment of the present invention is shown in FIG. In this circuit, delay circuits 61 to 6n are all connected in series. In this case, for example, the delay time of the delay circuit 63 is the delay time of the delay circuit 6h6.
It becomes the sum of 2. Therefore, the delay times of the respective delay circuits do not necessarily have to be different and may be the same.

In addition, the selection circuit 40 control signal 5 can be generated in various ways according to each system, such as a method of generating control signals by rewriting the contents of a register provided inside the integrated circuit, or a method of inputting all control signals directly from an external circuit. That's fine.

As explained in detail above, the circuit according to the present invention effectively prevents noise even when the normal input i and noise are input, even when the pulse width of the noise is different.
Only normal signals can be fully output. This circuit can be applied to cases where various types of noise are input from the outside of the integrated circuit, or when noise generated from inside the integrated circuit is input. It is versatile when connecting, and it is also possible to incorporate all of the extremely diverse circuits and circuits into an integrated circuit, and to install this circuit in front of the circuits in the integrated circuit that input all of their outputs, making it possible to integrate complex circuit configurations. It is advantageous for

[Brief explanation of drawings]

Figure 1 is a diagram showing a conventional circuit, Figures 4 and 6 are diagrams each showing an embodiment of the invention, and Figures 2, 3, and 5 are timing diagrams for explaining the operation. It is a chart diagram. 1...Input terminal, 21~2n, 6t~6n...
・・・Delay circuit, 3...;・Judgment circuit, 4...
...Selection circuit, 5...Control signal. Figure 1 23 Figure 4 1 Figure 2 Figure 3 Figure 6

Claims (1)

[Claims] a plurality of delay circuits that delay all input signals from input terminals; a selection circuit that selects all one of the outputs of the delay circuits; and a selection circuit that receives the output signal of the selection circuit and the input signal of the input terminal, and 1. A noise prevention circuit in an integrated circuit, comprising a determination circuit that blocks passage of an input signal at an input terminal when the signal is noise.