JPH0310546A - Signal reception system - Google Patents

Abstract

PURPOSE:To attain sure reception without recognizing leading of a signal for plural number of times by recognizing a received signal to be a significant signal when the consecutive time of the received signal is counted and when the time is consecutive for a prescribed time or over. CONSTITUTION:Plural flip-flops 23 to synchronize an input signal, a counter 24 counted up while its output is a prescribed value such as logical '1' in response to the output of the said synchronizing flip-flops 23 and a flip-flop 25 latching an overflow signal 0V of the said counter are provided to a high speed device 2. The counter 24 counts a clock CLK only when an output of the synchronizing flip-flops 23 is logical '1'. When the output of the synchronizing flip-flops 23 is consecutively logical '1', the count of the counter 24 reaches all 1s and an overflow signal 0V is outputted, then the flip-flop 25 is latched synchronously with the clock CLK.

Description

[Detailed Description of the Invention] [Summary] Regarding the signal reception method between devices with significantly different operating speeds, in order to prevent the rise of a signal from a low-speed device from being recognized multiple times, the above-mentioned method is applied to a high-speed device. one or more flip-flops that synchronize signals based on a high-speed clock; a counter that counts the time during which the output of the flip-flops continues to be a predetermined value based on the high-speed clock; and a counter for the counter. The present invention is characterized in that it includes a circuit that recognizes that the signal has been received when the numerical value reaches a predetermined value.

[Industrial application field]

The present invention relates to a signal reception method between devices having significantly different operating speeds (clock speeds).

[Prior art and its problems]

In the conventional signal transmission and reception between digital devices, since the clock frequencies of the devices are generally the same, it is often necessary to pay attention only to synchronization.

However, in recent years, devices using ultra-high-speed devices such as Josephson devices and HEMT devices have been realized, but on the other hand, the peripheral devices and control devices connected to these devices are still using old-fashioned devices. There are many cases where the speed ratio of the re-equipment is one to three digits or more.

In such a case, from the perspective of the high-speed device, the signal from the low-speed device appears to be changing slowly, and in the conventional circuit shown in FIG. 2, a problem as shown in FIG. 3 occurs.

In FIG. 2, 1 is a low-speed device, 2 is a high-speed device, 11 is a low-speed clock generation circuit, 21 is a high-speed clock generation circuit,
12 is an output stage flip-flop on the low-speed device side, and 22 is an input stage flip-flop on the high-speed device side.

In FIG. 3, CLK is the output of the high-speed clock generating circuit 21, 5TRT is the output waveform of the output stage flip-flop 12, and RCV is the output waveform of the input stage flip-flop 22.

As shown in FIG. 3, the slowly changing signal has a threshold level S
Since the time spent in the vicinity of the HL is long, if a slight level fluctuation or noise is superimposed during that time, the output of the input flip-flop 22 will change accordingly. Therefore, although the signal rises once on the output side, it may appear that the signal rises twice on the receiving side.

The present invention aims to prevent such inconveniences.

[Means to solve the problem]

In the present invention, the duration of the received signal is counted, and only when the duration of the received signal continues for a certain period of time or more is it recognized as a significant signal.

[Effect]

By doing this, even if the input signal fluctuates near the frequency hold level and is latched by the input stage flip-flop, it will be ignored if it lasts for a short time, and if it continues for a certain period of time or more, it will be ignored. Only in this case can it be recognized as a significant signal.

〔Example〕

FIG. 1 shows a circuit according to an embodiment of the present invention, in which a high-speed device 2 includes a plurality of flip-flops 23 (three stages in the illustrated example) and an output of the synchronizing flip-flops 23. A counter 24 that counts up while its output is at a predetermined value, for example, logic "1" in response to the above, and a flip-flop 25 that latches the overflow signal 0 of the counter are provided.

The counter 24 counts the clock CLK only when the output of the synchronization flip-flop 23 is "1". If the output of the flip-flop 23 reaches rOJ before the count value becomes all "1", the counter 24 is reset. The output of the flip-flop 23 continues to be “1”
When the count value of the counter 24 reaches all "1" and an overflow signal 0■ is output, the flip-flop 25 latches it in synchronization with the clock CLK.

〔effect〕

As described above, according to the present invention, even when a signal from a low-speed device changes slowly, an ultra-high-speed device can reliably receive the signal without recognizing the rise of the signal multiple times.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIGS. 2 and 3 are explanatory diagrams of the prior art. In the figure, 1 is a low-speed device, 2 is a high-speed device, 23 is a synchronization flip-flop on the receiving side, 24 is a counter, and 25 is a flip-flop for recognizing the received signal.

Claims (1)

[Claims] A signal from a first device (1) that operates with a relatively low-speed first clock is transmitted to a second device (2) that operates with a relatively high-speed second clock. ), the second device (2) includes one or more flip-flops (23) that synchronize the signal based on a second clock.
), a counter (24) for counting the time during which the output of the flip-flop continues to be at a predetermined value based on the second clock; A signal receiving system comprising: a circuit (25) for recognizing that a signal has been received.